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functional.\n\nThis project provides 2 HAL crates to provide [embassy-rs] with support for the AMD [Zynq™ 7000] SoC and the AMD [Zynq UltraScale+™ MPSoC]/[Zynq UltraScale+™ RFSoC].\n\n## About The Zynq™ SoCs\n\nThe AMD (formally Xilinx) Zynq™ SoCs are devices that combine an SoC core/cores (referred to as the PS or Programmable System) with FPGA fabric (referred to as the PL or Programmable Logic) as such they are \"hybrid\" devices.\n\nThe flow for getting a Zynq™ device up and running is fairly complicated, and involves core configuration along with custom hardware via an HDL design done in [Vivado], along with either a [PetaLinux] image or some other bare metal application done in C or C++ from [Vitis], this is then packaged together into an image the Zynq™ boots from.\n\nThe HDL design is **required** for the Zynq™ to start up at all, as it is responsible for setting up the core, along with it's peripheral configuration and placement.\n\n\u003e [!IMPORTANT]\n\u003e **A Note about the PL**\n\u003e\n\u003e On the Zynq™ devices, the PL is connected to the PS via some [AXI] interfaces, and as the hardware\n\u003e on the PL is entirely custom, we can't provide fully wrapped devices or register definitions\n\u003e configuration for it.\n\n## `embassy-zynq-7000`\n\nThe [`embassy-zynq-7000`] crate provides the HAL for the [Zynq™ 7000].\n\nThe Zynq™ 7000 itself comes in 2 variants SoC wise that we care about, the 7000 and the 7000S:\n\n* 7000S - Single-core ARM Cortex-A9 MPCore™\n* 7000 - Dual-core ARM Cortex-A9 MPCore™\n\n## `embassy-zynq-usplus`\n\n\u003e [!WARNING]\n\u003e This is just a stub, it won't really be worked on until the [`embassy-zynq-7000`] HAL is\n\u003e somewhat functional.\n\nThe [`embassy-zynq-usplus`] crate provides the HAL for the [Zynq UltraScale+™ MPSoC] and [Zynq UltraScale+™ RFSoC] family of devices.\n\nThe MPSoC has 3 variants, the CG, EG, and EV, core-wise we can group the EG and EV, so the following 2 configurations are what we care about:\n\n* CG\n  * Dual-core Arm Cortex-A53 MPCore™\n  * Dual-core Arm Cortex-R5F MPCore™\n* EG/EV\n  * Quad-core Arm Cortex-A53 MPCore™\n  * Dual-core Arm Cortex-R5F MPCore™\n  * Arm Mali-400 MP2 GPU\n\nIn addition, the EV variants of the MPSoC has hardware H.264/H.265.\n\nThe RFSoC has a core configuration of:\n\n* Quad-core Arm Cortex-A53 MPCore™\n* Dual-core Arm Cortex-R5F MPCore™\n\n## License\n\nThe Zynq™ 7000 and Zynq UltraScale+™ HALs for embassy are licensed under the [BSD-3-Clause] license. The full text of which can be found in the [`LICENSE`] file.\n\n[embassy-rs]: https://embassy.dev/\n[Zynq™ 7000]: https://www.amd.com/en/products/adaptive-socs-and-fpgas/soc/zynq-7000.html\n[Zynq UltraScale+™ MPSoC]: https://www.amd.com/en/products/adaptive-socs-and-fpgas/soc/zynq-ultrascale-plus-mpsoc.html\n[Zynq UltraScale+™ RFSoC]: https://www.amd.com/en/products/adaptive-socs-and-fpgas/soc/zynq-ultrascale-plus-rfsoc.html\n[Vivado]: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado.html\n[PetaLinux]: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/embedded-software/petalinux-sdk.html\n[Vitis]: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vitis.html\n[`embassy-zynq-7000`]: ./embassy-zynq-7000/\n[`embassy-zynq-usplus`]: ./embassy-zynq-usplus/\n[BSD-3-Clause]: https://spdx.org/licenses/BSD-3-Clause.htm\n[`LICENSE`]: ./LICENSE\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flethalbit%2Fembassy-zynq","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Flethalbit%2Fembassy-zynq","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flethalbit%2Fembassy-zynq/lists"}