{"id":16105449,"url":"https://github.com/lironmiz/nand2tetriscourse","last_synced_at":"2025-04-02T09:43:39.325Z","repository":{"id":135521884,"uuid":"603184323","full_name":"lironmiz/nand2tetrisCourse","owner":"lironmiz","description":"acadamic course in campus il about building a modern computer from basic logic gates such as \"nand\" to a general computer architecture that is designed execute any program such as \"Tetris\".  and also building assambler","archived":false,"fork":false,"pushed_at":"2023-03-05T03:22:17.000Z","size":103,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-04-02T04:42:27.099Z","etag":null,"topics":["adders","assembler","assembly","boolean-algebra","boolean-arithmetic","clock","code-generation","computer-architecture","course","cpu","cycles","flip-flops","hardware-description-language","learning-by-doing","logic-gates","machine-language","memory-units","parsing","project","register"],"latest_commit_sha":null,"homepage":"https://courses.campus.gov.il/courses/course-v1:HUJI+ACD_HUJI_nand2tetris+2020_1/course/","language":"Scilab","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/lironmiz.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-02-17T19:49:30.000Z","updated_at":"2023-04-11T16:12:19.000Z","dependencies_parsed_at":"2023-04-18T23:46:27.271Z","dependency_job_id":null,"html_url":"https://github.com/lironmiz/nand2tetrisCourse","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lironmiz%2Fnand2tetrisCourse","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lironmiz%2Fnand2tetrisCourse/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lironmiz%2Fnand2tetrisCourse/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lironmiz%2Fnand2tetrisCourse/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/lironmiz","download_url":"https://codeload.github.com/lironmiz/nand2tetrisCourse/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246794027,"owners_count":20834931,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["adders","assembler","assembly","boolean-algebra","boolean-arithmetic","clock","code-generation","computer-architecture","course","cpu","cycles","flip-flops","hardware-description-language","learning-by-doing","logic-gates","machine-language","memory-units","parsing","project","register"],"created_at":"2024-10-09T19:09:37.580Z","updated_at":"2025-04-02T09:43:39.286Z","avatar_url":"https://github.com/lironmiz.png","language":"Scilab","funding_links":[],"categories":[],"sub_categories":[],"readme":"\u003ca name=\"readme-top\"\u003e\u003c/a\u003e\n\u003ch1 align=\"center\"\u003e 🧠 nand2tetrisCourse 🧠 \u003c/h1\u003e\n\n\u003cimg src=\"https://i.imgur.com/dBaSKWF.gif\" height=\"50\" width=\"100%\"\u003e\n\nthe course is on building a modern computer from basic logic gates to a general computer architecture capable of executing programs such as \"Tetris\".\n\nduring the course i was learn how to design and build all the hardware components (chips) using a hardware description language taught in the course. I was responsible for building these components from scratch and testing them using a hardware simulator provided along with the course materials. This hands-on experience was provided me with an in-depth understanding of the computer's inner workings. Additionally, I will also learn how to build an assembler program to translate programs written in symbolic language into binary code. This skill will enable me to program my computer and execute my own code.\n\nBy the end of this course, I will have the knowledge and practical experience necessary to build a fully functional computer and write my own programs. This is a challenging but rewarding course that will provide me with a unique understanding of how computers work.\n\nCourse instructors:\n\nProf. Shimon Shoken, Interdisciplinary Center\n\nNoam Nissan, Hebrew University\n\n\u003c!-- Badges --\u003e\n\u003cp\u003e\n  \u003ca href=\"https://github.com/lironmiz/nand2tetrisCourse/graphs/contributors\"\u003e\n    \u003cimg src=\"https://img.shields.io/github/contributors/lironmiz/nand2tetrisCourse\" alt=\"contributors\" /\u003e\n  \u003c/a\u003e\n  \u003ca href=\"\"\u003e\n    \u003cimg src=\"https://img.shields.io/github/last-commit/lironmiz/nand2tetrisCourse\" alt=\"last update\" /\u003e\n  \u003c/a\u003e\n  \u003ca href=\"https://github.com/lironmiz/nand2tetrisCourse/network/members\"\u003e\n    \u003cimg src=\"https://img.shields.io/github/forks/lironmiz/nand2tetrisCourse\" alt=\"forks\" /\u003e\n  \u003c/a\u003e\n  \u003ca href=\"https://github.com/lironmiz/nand2tetrisCourse/stargazers\"\u003e\n    \u003cimg src=\"https://img.shields.io/github/stars/ladunjexa/nand2tetrisCourse\" alt=\"stars\" /\u003e\n  \u003c/a\u003e\n  \u003ca href=\"https://github.com/lironmiz/nand2tetrisCourse/issues/\"\u003e\n    \u003cimg src=\"https://img.shields.io/github/issues/lironmiz/nand2tetrisCourse\" alt=\"open issues\" /\u003e\n  \u003c/a\u003e\n  \u003ca href=\"https://github.com/lironmiz/nand2tetrisCourse/language count/\"\u003e\n    \u003cimg src=\"https://img.shields.io/github/languages/count/lironmiz/nand2tetrisCourse\" alt=\"language count\" /\u003e\n  \u003c/a\u003e\n\u003c/p\u003e\n\n ![](https://img.shields.io/tokei/lines/github/lironmiz/nand2tetrisCourse?color=blue\u0026label=Lines%20of%20Code)\n![Size](https://img.shields.io/github/repo-size/lironmiz/nand2tetrisCourse?color=red\u0026label=Repo%20Size%20)\n \u003cimg src=\"https://img.shields.io/github/languages/top/lironmiz/nand2tetrisCourse\" alt=\"top language\" /\u003e\n\n\u003c!-- Table of Contents --\u003e\n\u003cdetails\u003e\n\n\u003csummary\u003e\n\n# :notebook_with_decorative_cover: Table of Contents\n\n\u003c/summary\u003e\n\n- [The Graduation Certificate](#star2-the-graduation-certificate)\n- [Course Material](#books-course-material) \n- [Course Summary](#alien-course-summary) \n- [Contact](#handshake-contact)\n- [Acknowledgements](#gem-acknowledgements)\n- [About the authors](#telephone-about-the-authors)\n- [Project Status](#octocat-project-status)\n\n\u003c/details\u003e  \n\n\u003c!-- The Graduation Certificate --\u003e\n# :star2: The Graduation Certificate \n\n\u003cp align=\"right\"\u003e(\u003ca href=\"#readme-top\"\u003eback to top\u003c/a\u003e)\u003c/p\u003e\n\n\u003c!-- Course Material --\u003e\n# :books: Course Material\n \n    + Introduction to building systems\n    + Language Description Hardware\n    + Boolean algebra\n    + building basic logic gates\n    + Binary representation of numbers\n    + Boolean arithmetic\n    + Building adders and an algebraic-logic unit (ALU)\n    + Time representation\n    + Clock cycles\n    + Flip-flop gates\n    + Construction of registers and memory units (ROM, RAM) \n    + Machine language: symbolic representation, binary \n    + Writing and running programs in a low level programming language.\n    + Computer architectures\n    + Central processing unit\n    + Management of input/output units\n    + Building a processor \n    + Translation of programs: syntax, semantics, parsing, code generation, symbol tables\n    + Assembler development\n\n\u003cp align=\"right\"\u003e(\u003ca href=\"#readme-top\"\u003eback to top\u003c/a\u003e)\u003c/p\u003e\n\n\u003c!-- The Course Summary --\u003e\n# :alien: Course Summary\n\n## 1. TABLE OF CONTENTS\n  - [1. TABLE OF CONTENTS](#1-table-of-contents)\n  - [2. BOOLEAN VALUES](#2-boolean-values)\n  - [3. BOOLEAN VARIABLES](#3-boolean-variables)\n  - [4. BOOLEAN FUNCTIONS](#4-boolean-functions)\n  - [5. BOOLEAN ALGEBRA](#5-boolean-algebra)\n  - [6. DISJUNCTIVE NORMAL FORM](#6-disjunctive-normal-form)\n  - [7. NAND](#7-nand)\n  - [8. LOGIC GATES](#8-logic-gates)\n  - [9. HARDWARE DESCRIPTION LANGUAGE](#9-hardware-sescription-language)\n  - [10. BUSES](#10-buses)\n  - [11. MULTIPLEXOR](#11-multiplexor)\n  - [12. DEMULTIPLEXOR](#12-demultiplexor)\n  - [13. PROJECT1](#13-project1)\n  - [14. ALU](#14-alu)\n  - [15. NUMERAL SYSTEM](#15-numeral-system)\n  - [16. BINARY NUMBERS](#16-binary-numbers)\n  - [17. BINARY ARITHMETIC](#17-binary-arithmetic)\n  - [18. HACK ALU](#18-hack-alu)\n  - [19. PROJECT2](#19-project2)\n## 2. BOOLEAN VALUES\n\n![TrueOrFalseAndyCohenGIF (2)](https://user-images.githubusercontent.com/91504420/219793288-c281cd34-9b91-4b79-8412-3118b2af6549.gif)\n\nA Boolean value is a data type that has two possible values, either \"true\" or \"false\". Boolean values are often used in programming to make decisions, comparisons, and to control program flow.\n\n![image](https://user-images.githubusercontent.com/91504420/219793033-d9ea42c7-bc0d-4fd5-b7bb-267eb00a2128.png)\n\n## 3. BOOLEAN VARIABLES\n\n![ThereAreSoManyVariablesInPlayDavidRoseGIF](https://user-images.githubusercontent.com/91504420/219793867-04f1d601-8edb-4c42-9b1b-6d01dd7b4583.gif)\n\nA Boolean variable is a variable that can store a Boolean value. It is a variable that can only hold the value \"true\" or \"false\". Boolean variables are often used to represent conditions, such as whether a condition is true or false.\n\n## 4. BOOLEAN FUNCTIONS\n\n![JojiFilthyFrankGIF](https://user-images.githubusercontent.com/91504420/219794233-5c49a45a-ce0d-419b-8034-3cfae1d849b3.gif)\n\nA Boolean function is a function that takes one or more Boolean values as input and produces a single Boolean value as output. Boolean functions are used to perform logical operations on Boolean values. Some common Boolean functions include AND, OR, NOT, XOR, and NAND. These functions are used to combine, negate, or compare Boolean values to determine whether a given condition is true or false.\n\n![image](https://user-images.githubusercontent.com/91504420/219794330-e9b0925f-abad-4d8d-afee-ed1c2ae76d47.png)\n\n## 5. BOOLEAN ALGEBRA\n\n![AWholeNewWorldAladdinGIF](https://user-images.githubusercontent.com/91504420/219796635-97f6dde2-a09a-46cb-bcc5-d2313a11100f.gif)\n\noolean algebra is a branch of mathematics that deals with logical operations on true or false values, which are represented as 1 and 0, respectively. It is an algebraic system that is used to represent logical propositions and analyze their properties.\n\nHere's a summary of some of the key concepts in Boolean algebra:\n\nBoolean operators: The three primary Boolean operators are AND, OR, and NOT. These operators are used to perform logical operations on Boolean values.\n\nBoolean expressions: A Boolean expression is a combination of Boolean variables and operators that evaluates to a Boolean value. For example, the expression \"A AND B\" is a Boolean expression that is true only if both A and B are true.\n\nTruth tables: A truth table is a table that lists all possible combinations of inputs for a Boolean expression and the resulting output. Truth tables are used to analyze and evaluate Boolean expressions.\n\nLaws of Boolean algebra: There are several laws of Boolean algebra, including the commutative, associative, distributive, and identity laws. These laws provide a set of rules that can be used to simplify and manipulate Boolean expressions.\n\nBoolean functions: A Boolean function is a function that takes one or more Boolean values as input and produces a single Boolean value as output. Boolean functions are used to perform logical operations on Boolean values.\n\nBoolean algebra is an important concept in computer science and digital electronics, and is used extensively in the design and analysis of digital circuits and systems.\n\n| Law                  | Equation                              |\n|----------------------|---------------------------------------|\n| Commutative Law      | A AND B = B AND A \u003cbr\u003e A OR B = B OR A |\n| Associative Law      | (A AND B) AND C = A AND (B AND C) \u003cbr\u003e (A OR B) OR C = A OR (B OR C) |\n| Distributive Law     | A AND (B OR C) = (A AND B) OR (A AND C) \u003cbr\u003e A OR (B AND C) = (A OR B) AND (A OR C) |\n| Identity Law         | A AND 1 = A \u003cbr\u003e A OR 0 = A |\n| Negation Law         | A AND NOT A = 0 \u003cbr\u003e A OR NOT A = 1 |\n| Double Negation Law  | NOT (NOT A) = A |\n| De Morgan's Law      | NOT (A AND B) = (NOT A) OR (NOT B) \u003cbr\u003e NOT (A OR B) = (NOT A) AND (NOT B) |\n| Absorption Law       | A OR (A AND B) = A \u003cbr\u003e A AND (A OR B) = A |\n\n## 6. DISJUNCTIVE NORMAL FORM\n\n![ICanDoItJonTafferGIF](https://user-images.githubusercontent.com/91504420/219798501-6e9022af-4cdf-4ba0-a004-d60dd3830b9f.gif)\n\nDNF stands for Disjunctive Normal Form, which is a way to represent a Boolean function as the logical OR of multiple AND terms. In other words, it is a way to express a Boolean function as a sum of products.\n\nTo convert a Boolean expression to DNF, one needs to:\n\nExpand the expression into a sum of minterms, which are the product terms that evaluate to 1 for the given combination of input variables.\nCombine the minterms with logical OR operator to obtain the DNF.\nDNF is useful in digital circuit design because it provides a way to represent a Boolean function in a form that is amenable to logic gate implementation. Additionally, DNF can be used to find the minimal sum-of-products representation of a Boolean function, which is the expression that uses the smallest number of terms and literals to represent the function.\n\n## 7. NAND\n\n![IveGotThePowerJimCarreyGIF](https://user-images.githubusercontent.com/91504420/219799684-e8cd5755-6363-4b97-b4b1-b1a64b1e04be.gif)\n\nNAND (not-and) is a logical operation in Boolean algebra that returns a FALSE output only when both of its inputs are TRUE, and returns a TRUE output for all other input combinations. In other words, it is the negation of the logical AND operation.\n\nNAND is a universal gate, which means that any Boolean function can be expressed using NAND gates only. This is because NAND can be used to implement all the other basic Boolean operations such as NOT, AND, OR, and XOR. In fact, it is possible to construct an entire digital circuit using only NAND gates.\n\nNAND gates are widely used in digital circuit design because they are relatively simple to implement and provide a compact and efficient way to represent Boolean functions. Additionally, NAND gates have the property of logical equivalence, which means that any Boolean expression can be transformed into an equivalent expression using only NAND gates, without changing the logical function that it represents.\n\n![image](https://user-images.githubusercontent.com/91504420/219799749-80dbab6e-b972-42f2-a47a-0552ff7fc808.png)\n\n## 8. LOGIC GATES\n\n![FeelMeThinkAboutItGIF](https://user-images.githubusercontent.com/91504420/219811381-fdb32fc6-be9c-48c9-a76c-ebeb38e129fd.gif)\n\nLogic gates are electronic circuits that perform logical operations on one or more binary inputs to produce a single binary output. They are the building blocks of digital circuits and computers, and are used to implement Boolean algebraic functions in electronic devices.\n\nThere are several types of logic gates, including:\n\n+ NOT gate: also known as an inverter, it produces an output that is the opposite of its input.\n\n+ AND gate: it produces an output of 1 only when all of its inputs are 1.\n\n+ OR gate: it produces an output of 1 when any of its inputs are 1.\n\n+ XOR gate: it produces an output of 1 when exactly one of its inputs is 1.\n\n+ NAND gate: it produces an output of 0 only when all of its inputs are 1, otherwise it produces an output of 1.\n\n+ NOR gate: it produces an output of 0 when any of its inputs are 1, otherwise it produces an output of 1.\n\nLogic gates are used to build more complex circuits such as adders, multipliers, memory units, and microprocessors. The design of digital circuits using logic gates is an important part of computer engineering and is used in various fields, including robotics, communications, and control systems.\n\n## 9. HARDWARE DESCRIPTION LANGUAGE\n\n![GandalfICanHelpGIF](https://user-images.githubusercontent.com/91504420/219812841-d3f23138-65a7-4851-90c8-aa509adb1536.gif)\n\nIn computer science, HDL stands for Hardware Description Language. It is a specialized programming language used to design and describe digital circuits and systems at the register-transfer level (RTL). HDLs are used to specify the behavior of digital circuits and can be used to simulate, verify, and synthesize digital circuits. HDLs are used to create designs for logic gates and other digital components, and can be used to describe the structure and functionality of entire digital systems. Some popular HDLs include Verilog and VHDL.\n\n![image](https://user-images.githubusercontent.com/91504420/219812413-37cdbe74-b3f3-41cb-9204-893dc5101d7f.png)\n\n![image](https://user-images.githubusercontent.com/91504420/219813215-ce5d2b40-bccb-48ae-aa90-69929fb95a86.png)\n\n![image](https://user-images.githubusercontent.com/91504420/219814345-3e1ca794-12e4-43fc-94b2-0bf2b0fe852c.png)\n\n![image](https://user-images.githubusercontent.com/91504420/219814949-ca088a4d-e871-4faf-a1d0-fd5e2b85938d.png)\n\n![image](https://user-images.githubusercontent.com/91504420/219815457-8b8f06a2-5a14-476f-b430-b4407d14308d.png)\n\n## 10. BUSES\n\n![LittleBitOfThisLittleBitOfThatMarissaRachelGIF](https://user-images.githubusercontent.com/91504420/219816902-7a6d3474-934f-4a6e-8a91-c4b1f65d4996.gif)\n\nIn computer architecture and digital electronics, a bus of bits refers to a collection of wires or conductors that carry multiple bits of data in parallel. Buses of bits are used to transfer data and signals between different components or devices within a computer or electronic system. The size of a bus of bits, commonly referred to as its width, is measured in bits and determines the maximum amount of data that can be transferred in a single clock cycle.\n\nBuses of bits can be classified based on their purpose, such as data buses, address buses, control buses, and expansion buses. They are commonly used in microprocessors, memory systems, and other digital circuits where high-speed data transfer is required. Buses of bits are an essential component of digital systems and play a critical role in determining the performance and capabilities of the system.\n\n![image](https://user-images.githubusercontent.com/91504420/219816955-c952856f-ee00-493f-9b0c-6e763fffbd61.png)\n\n![image](https://user-images.githubusercontent.com/91504420/219817195-e111a2c2-0144-4445-b8a9-07ff2c59da85.png)\n\n## 11. MULTIPLEXOR\n\n![DependsOnTheMoodDeanSchneiderGIF](https://user-images.githubusercontent.com/91504420/219818930-7e43b405-62e7-4299-a615-258f132ab158.gif)\n\nIn digital electronics and computer architecture, a multiplexer (also known as a MUX) is a device that selects one of several input signals and forwards it to a single output line. A multiplexer operates by using a set of control inputs to determine which of the input signals should be routed to the output.\n\nMultiplexers are commonly used in digital circuits to reduce the number of wires required to transmit data, as well as to select between different sources of data or signals. They are often used in combination with demultiplexers to transmit and receive data over shared communication lines.\n\nMultiplexers are available in a range of sizes, typically based on the number of input signals that they can handle. Common examples include 2-to-1, 4-to-1, 8-to-1, and 16-to-1 multiplexers. Multiplexers are widely used in digital design and play a critical role in many modern electronic systems.\n\n![image](https://user-images.githubusercontent.com/91504420/219818879-e6bfd432-e82a-4eef-933f-a45e3236a10d.png)\n\n![image](https://user-images.githubusercontent.com/91504420/219819237-59fbbe7e-7c31-4fa1-8415-effaa9602ac3.png)\n\n## 12. DEMULTIPLEXOR\n\n![ThisIsSoSimilarYetDifferentRachelSmithGIF](https://user-images.githubusercontent.com/91504420/219819407-1d301f42-95ce-4bf5-bb35-75b4a9eccaa0.gif)\n\nIn digital electronics and computer architecture, a demultiplexer (also known as a DEMUX) is a device that takes a single input signal and routes it to one of several output lines based on a set of control inputs. A demultiplexer is essentially the reverse of a multiplexer, which takes several input signals and selects one of them to be forwarded to a single output line.\n\nA demultiplexer is commonly used to expand the capacity of a shared communication line, allowing multiple data streams to be transmitted and received over a single channel. Demultiplexers can also be used to route signals to different processing units or to control the flow of data within a larger system.\n\nLike multiplexers, demultiplexers are available in a range of sizes based on the number of output lines they can handle, such as 1-to-2, 1-to-4, and 1-to-8 demultiplexers. Demultiplexers play a critical role in digital design and are widely used in many modern electronic systems.\n\n![image](https://user-images.githubusercontent.com/91504420/219819424-56086abd-990d-4f96-a3f1-ba1aba541c62.png)\n\n![image](https://user-images.githubusercontent.com/91504420/219819651-6055ac67-855e-4be4-9962-2048a1cebe20.png)\n\n## 13. PROJECT1\n\n### not logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/Not.hdl\n\n/**\n * Not gate:\n * out = not in\n */\nCHIP Not {\n    IN in;\n    OUT out;\n\n    PARTS:\n    Nand(a=in, b=in, out=out);\n}\n```\n### output file not gate:\n\n![image](https://user-images.githubusercontent.com/91504420/219874107-65376354-24e1-4467-8976-53c55dc371b6.png)\n\n### compare file not gate:\n\n![image](https://user-images.githubusercontent.com/91504420/219874153-4acbd951-f39c-4cf8-afef-497ced0f7ad7.png)\n\n### not gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/221359570-3d4ea240-595b-47d9-b5b0-a741d6fe4536.png)\n\n### or logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/Or.hdl\n\n /**\n * Or gate:\n * out = 1 if (a == 1 or b == 1)\n *       0 otherwise\n */\n\nCHIP Or {\n    IN a, b;\n    OUT out;\n\n    PARTS:\n\tNot(in=a, out=notA);\n\tNot(in=b, out=notB);\n\tNand(a=notA, b=notB, out=out);\n}\n```\n### output file or gate:\n\n![image](https://user-images.githubusercontent.com/91504420/219874642-0db5421a-917d-4e9d-bace-57acf4807b68.png)\n\n\n### compare file or gate:\n\n![image](https://user-images.githubusercontent.com/91504420/219874663-37949581-6ff1-423e-99fb-0a113dfd019c.png)\n\n### or gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/221359454-489cee0d-3fdc-4dd6-ad30-5f6bf2c43cb4.png)\n\n### and logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/And.hdl\n\n/**\n * And gate: \n * out = 1 if (a == 1 and b == 1)\n *       0 otherwise\n */\n\nCHIP And {\n    IN a, b;\n    OUT out;\n\n    PARTS:\n\tNand(a=a, b=b, out=nandOutput);\n\tNot(in=nandOutput, out=out);\n}\n```\n### output file and gate:\n![image](https://user-images.githubusercontent.com/91504420/219875022-8906f2f6-b168-43cf-832e-dce1d6c8f97c.png)\n\n\n### compare file and gate:\n\n![image](https://user-images.githubusercontent.com/91504420/219875032-3051ae3e-fc3c-46d2-bdba-4bce5f3fbf8b.png)\n\n### and gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/221359276-d9e2e41a-90c5-4597-bbae-53793455239c.png)\n\n\n### xor logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/Xor.hdl\n\n/**\n * Exclusive-or gate:\n * out = not (a == b)\n */\n\nCHIP Xor {\n    IN a, b;\n    OUT out;\n\n    PARTS:\n    Or(a=a, b=b, out=c1);\n    Nand(a=a, b=b, out=c2);\n    And(a=c1, b=c2, out=out);\n}\n```\n### output file xor gate:\n\n![image](https://user-images.githubusercontent.com/91504420/221358965-659583d4-964b-40d2-bde3-3df6f7626a6e.png)\n\n\n### compare file xor gate:\n\n![image](https://user-images.githubusercontent.com/91504420/221358955-8bb0dd5d-5dee-47ff-95a8-f7435b7942ae.png)\n\n### xor gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/221359035-dae063c8-61d6-4415-986d-412d98302612.png)\n\n### mux logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/Mux.hdl\n\nCHIP Mux {\n    IN a, b, sel;\n    OUT out;\n\n    PARTS:\n    Not(in=sel, out=nsel);\n    And(a=sel, b=b, out=c1);\n    And(a=nsel, b=a, out=c2);\n    Or(a=c1, b=c2, out=out);\n}\n```\n### output file mux gate:\n\n![image](https://user-images.githubusercontent.com/91504420/221359966-83d84e82-29b1-48eb-a544-b2143d9bf75b.png)\n\n\n### compare file mux gate:\n\n![image](https://user-images.githubusercontent.com/91504420/221359985-7187eb7a-10cb-4c67-bc9c-71163fafc368.png)\n\n### mux gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/221359874-a47e1017-1769-47f7-be9b-ce0b74020a41.png)\n\n### dmux logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/DMux.hdl\n\n/**\n * Dmultiplexor.  \n * {a,b} = {in,0} if sel == 0\n *         {0,in} if sel == 1\n */\n\nCHIP DMux {\n    IN in, sel;\n    OUT a, b;\n\n    PARTS:\n    Not(in=sel, out=nsel);\n    And(a=nsel, b=in, out=a);\n    And(a=sel, b=in, out=b);\n}\n```\n### output file dmux gate:\n\n![image](https://user-images.githubusercontent.com/91504420/221361245-42dd395f-1fc1-4b1b-bfda-56d063ebc25d.png)\n\n### compare file dmux gate:\n\n![image](https://user-images.githubusercontent.com/91504420/221361255-a55a1334-668f-42d5-bfa0-c138d498a7ed.png)\n\n### dmux gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/221361137-00d926db-2d3b-424d-b22e-4859310a7538.png)\n\n### not16 logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/Not16.hdl\n\n/**\n * 16-bit Not gate: for i = 0..15: out[i] = Not in[i]\n */\n\nCHIP Not16 {\n    IN in[16];\n    OUT out[16];\n\n    PARTS:\n    Nand(a=in[0], b=in[0], out=out[0]);\n    Nand(a=in[1], b=in[1], out=out[1]);\n    Nand(a=in[2], b=in[2], out=out[2]);\n    Nand(a=in[3], b=in[3], out=out[3]);\n    Nand(a=in[4], b=in[4], out=out[4]);\n    Nand(a=in[5], b=in[5], out=out[5]);\n    Nand(a=in[6], b=in[6], out=out[6]);\n    Nand(a=in[7], b=in[7], out=out[7]);\n    Nand(a=in[8], b=in[8], out=out[8]);\n    Nand(a=in[9], b=in[9], out=out[9]);\n    Nand(a=in[10], b=in[10], out=out[10]);\n    Nand(a=in[11], b=in[11], out=out[11]);\n    Nand(a=in[12], b=in[12], out=out[12]);\n    Nand(a=in[13], b=in[13], out=out[13]);\n    Nand(a=in[14], b=in[14], out=out[14]);\n    Nand(a=in[15], b=in[15], out=out[15]);\n}\n```\n### output file not16 gate:\n\n![image](https://user-images.githubusercontent.com/91504420/221362075-0ce2983f-e802-4d1d-8cd5-e547c2b5e089.png)\n\n### compare file not16 gate:\n\n![image](https://user-images.githubusercontent.com/91504420/221362090-aac4e65b-5e74-413f-a849-5626249a34c1.png)\n\n### not16 gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/221362670-d7d1c385-0f6b-44ff-9808-18746a0c299c.png)\n\n### and16 logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/And16.hdl\n\n/**\n * 16-bit-wise And gate: for i = 0..15: out[i] = a[i] And b[i]\n */\n\nCHIP And16 {\n    IN a[16], b[16];\n    OUT out[16];\n\n    PARTS:\n    And(a=a[0], b=b[0], out=out[0]);\n    And(a=a[1], b=b[1], out=out[1]);\n    And(a=a[2], b=b[2], out=out[2]);\n    And(a=a[3], b=b[3], out=out[3]);\n    And(a=a[4], b=b[4], out=out[4]);\n    And(a=a[5], b=b[5], out=out[5]);\n    And(a=a[6], b=b[6], out=out[6]);\n    And(a=a[7], b=b[7], out=out[7]);\n    And(a=a[8], b=b[8], out=out[8]);\n    And(a=a[9], b=b[9], out=out[9]);\n    And(a=a[10], b=b[10], out=out[10]);\n    And(a=a[11], b=b[11], out=out[11]);\n    And(a=a[12], b=b[12], out=out[12]);\n    And(a=a[13], b=b[13], out=out[13]);\n    And(a=a[14], b=b[14], out=out[14]);\n    And(a=a[15], b=b[15], out=out[15]);\n}\n```\n### output file and16 gate:\n\n![image](https://user-images.githubusercontent.com/91504420/221363510-a2ac3b7b-cf42-404d-a9dd-b1266c6e131c.png)\n\n### compare file and16 gate:\n\n![image](https://user-images.githubusercontent.com/91504420/221363525-d565bc8c-7237-4cb5-b1a1-b3397d49dadf.png)\n\n### and16 gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/221364210-6daaf116-24ba-430a-a93f-6d5b5c35d8b3.png)\n\n### mux16 logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/Mux16.hdl\n\n/**\n * 16-bit multiplexor. If sel == 1 then out = b else out = a.\n */\n\nCHIP Mux16 {\n    IN a[16], b[16], sel;\n    OUT out[16];\n\n    PARTS:\n    Mux(a=a[0], b=b[0], sel=sel, out=out[0]);\n    Mux(a=a[1], b=b[1], sel=sel, out=out[1]);\n    Mux(a=a[2], b=b[2], sel=sel, out=out[2]);\n    Mux(a=a[3], b=b[3], sel=sel, out=out[3]);\n    Mux(a=a[4], b=b[4], sel=sel, out=out[4]);\n    Mux(a=a[5], b=b[5], sel=sel, out=out[5]);\n    Mux(a=a[6], b=b[6], sel=sel, out=out[6]);\n    Mux(a=a[7], b=b[7], sel=sel, out=out[7]);\n    Mux(a=a[8], b=b[8], sel=sel, out=out[8]);\n    Mux(a=a[9], b=b[9], sel=sel, out=out[9]);\n    Mux(a=a[10], b=b[10], sel=sel, out=out[10]);\n    Mux(a=a[11], b=b[11], sel=sel, out=out[11]);\n    Mux(a=a[12], b=b[12], sel=sel, out=out[12]);\n    Mux(a=a[13], b=b[13], sel=sel, out=out[13]);\n    Mux(a=a[14], b=b[14], sel=sel, out=out[14]);\n    Mux(a=a[15], b=b[15], sel=sel, out=out[15]);\n}\n```\n### output file mux16 gate:\n\n![image](https://user-images.githubusercontent.com/91504420/221364502-33a569db-3b17-44c3-b88e-c1f02fb08867.png)\n\n### compare file mux16 gate:\n\n![image](https://user-images.githubusercontent.com/91504420/221364515-ffb7d18d-e11e-46b5-a1b6-fd8f1a4d5622.png)\n\n### mux16 gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/221367258-b8a0103b-7e5e-4a46-bba7-3058c72dc8e0.png)\n\n### or16 logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/Or16.hdl\n\n/**\n * 16-bit bitwise Or:\n * for i = 0..15 out[i] = (a[i] or b[i])\n */\n\nCHIP Or16 {\n    IN a[16], b[16];\n    OUT out[16];\n\n    PARTS:\n    Or(a=a[0], b=b[0], out=out[0]);\n\tOr(a=a[1], b=b[1], out=out[1]);\n\tOr(a=a[2], b=b[2], out=out[2]);\n\tOr(a=a[3], b=b[3], out=out[3]);\n\tOr(a=a[4], b=b[4], out=out[4]);\n\tOr(a=a[5], b=b[5], out=out[5]);\n\tOr(a=a[6], b=b[6], out=out[6]);\n\tOr(a=a[7], b=b[7], out=out[7]);\n\tOr(a=a[8], b=b[8], out=out[8]);\n\tOr(a=a[9], b=b[9], out=out[9]);\n\tOr(a=a[10], b=b[10], out=out[10]);\n\tOr(a=a[11], b=b[11], out=out[11]);\n\tOr(a=a[12], b=b[12], out=out[12]);\n\tOr(a=a[13], b=b[13], out=out[13]);\n\tOr(a=a[14], b=b[14], out=out[14]);\n\tOr(a=a[15], b=b[15], out=out[15]);\n}\n```\n### output file or16 gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222781812-a52a8cb8-4b71-4b11-8e1a-87987d915488.png)\n\n### compare file or16 gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222781897-8176e7e6-0aa8-41c8-8ae1-a01800841b11.png)\n\n### or16 gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/222782543-ea1a5ccf-760b-499e-8d95-0d1c6b997d9f.png)\n\n### or8Way logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/Or8Way.hdl\n\n/**\n * 8-way Or: \n * out = (in[0] or in[1] or ... or in[7])\n */\n\nCHIP Or8Way {\n    IN in[8];\n    OUT out;\n\n    PARTS:\n    Or(a=in[0], b=in[1], out=out01);\n\tOr(a=in[2], b=in[3], out=out23);\n\tOr(a=in[4], b=in[5], out=out45);\n\tOr(a=in[6], b=in[7], out=out67);\n\tOr(a=out01, b=out23, out=out0123);\n\tOr(a=out45, b=out67, out=out4567);\n\tOr(a=out0123, b=out4567, out=out);\n}\n```\n### output file or8Way gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222664243-2bf757c2-225d-4f71-9fd9-103fef20b76b.png)\n\n### compare file or8Way gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222664471-86fbab72-d133-40df-aa36-381a2ffc9951.png)\n\n### or8Way gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/222665000-b35e72d7-086e-4bc1-b7a6-740967d8aaae.png)\n\n### DMux4Way logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/DMux4Way.hdl\n\n/**\n * 4-way demultiplexor:\n * {a, b, c, d} = {in, 0, 0, 0} if sel == 00\n *                {0, in, 0, 0} if sel == 01\n *                {0, 0, in, 0} if sel == 10\n *                {0, 0, 0, in} if sel == 11\n */\n\nCHIP DMux4Way {\n    IN in, sel[2];\n    OUT a, b, c, d;\n\n    PARTS:\n    Not(in=sel[0], out=notsel0);\n    Not(in=sel[1], out=notsel1);\n    And(a=notsel0, b=notsel1, out=sela);\n    And(a=sela, b=in, out=a);\n    And(a=sel[0], b=notsel1, out=selb);\n    And(a=selb, b=in, out=b);\n    And(a=notsel0, b=sel[1], out=selc);\n    And(a=selc, b=in, out=c);\n    And(a=sel[0], b=sel[1], out=seld);\n    And(a=seld, b=in, out=d);\n}\n```\n### output file DMux4Way gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222669983-3ed3f593-ae52-48a3-89e2-fa9bf6f247d3.png)\n\n\n### compare file DMux4Way gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222670063-c91905e0-dd71-49db-b634-928d8f483d86.png)\n\n### DMux4Way gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/222669239-85f25d99-928e-4432-aca4-4cefcca02925.png)\n\n### DMux8Way logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/DMux8Way.hdl\n\n/**\n * 8-way demultiplexor:\n * {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000\n *                            {0, in, 0, 0, 0, 0, 0, 0} if sel == 001\n *                            etc.\n *                            {0, 0, 0, 0, 0, 0, 0, in} if sel == 111\n */\n\nCHIP DMux8Way {\n    IN in, sel[3];\n    OUT a, b, c, d, e, f, g, h;\n\n    PARTS:\n    Not(in=sel[0], out=notsel0);\n    Not(in=sel[1], out=notsel1);\n    Not(in=sel[2], out=notsel2);\n    And(a=notsel0, b=notsel1, out=sela1);\n    And(a=sela1, b=notsel2, out=sela);\n    And(a=sela, b=in, out=a);\n    And(a=sel[0], b=notsel1, out=selb1);\n    And(a=selb1, b=notsel2, out=selb);\n    And(a=selb, b=in, out=b);\n    And(a=notsel0, b=sel[1], out=selc1);\n    And(a=selc1, b=notsel2, out=selc);\n    And(a=selc, b=in, out=c);\n    And(a=sel[0], b=sel[1], out=seld1);\n    And(a=seld1, b=notsel2, out=seld);\n    And(a=seld, b=in, out=d);\n    And(a=notsel0, b=notsel1, out=sele1);\n    And(a=sele1, b=sel[2], out=sele);\n    And(a=sele, b=in, out=e);\n    And(a=sel[0], b=notsel1, out=self1);\n    And(a=self1, b=sel[2], out=self);\n    And(a=self, b=in, out=f);\n    And(a=notsel0, b=sel[1], out=selg1);\n    And(a=selg1, b=sel[2], out=selg);\n    And(a=selg, b=in, out=g);\n    And(a=sel[0], b=sel[1], out=selh1);\n    And(a=selh1, b=sel[2], out=selh);\n    And(a=selh, b=in, out=h);\n}\n```\n### output file DMux8Way gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222682871-a1816c60-d8f6-47eb-b810-a3046167eff6.png)\n\n\n### compare file DMux8Way gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222682970-46dd15ef-373f-4bdd-91d1-d04053a2f804.png)\n\n### DMux8Way gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/222685950-ebce3a0f-e5c7-4139-a8ae-2ea780d97252.png)\n\n### Mux4Way16 logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/Mux4Way16.hdl\n\n/**\n * 4-way 16-bit multiplexor:\n * out = a if sel == 00\n *       b if sel == 01\n *       c if sel == 10\n *       d if sel == 11\n */\n\nCHIP Mux4Way16 {\n    IN a[16], b[16], c[16], d[16], sel[2];\n    OUT out[16];\n\n    PARTS:\n    Mux16(a=a, b=b, sel=sel[0], out=outab);\n    Mux16(a=c, b=d, sel=sel[0], out=outcd);\n    Mux16(a=outab, b=outcd, sel=sel[1], out=out);\n}\n```\n\n### output file Mux4Way16 gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222688440-a72bf93b-fa98-4cad-bc04-b970d012560c.png)\n\n### compare file Mux4Way16 gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222689010-b9a5315c-16fe-48ac-9fbf-26eec0fad19e.png)\n\n### Mux4Way16 gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/222689584-8a9db23f-ccba-435e-b298-238c402a1965.png)\n\n### Mux8Way16 logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/01/Mux4Way16.hdl\n\n/**\n * 4-way 16-bit multiplexor:\n * out = a if sel == 00\n *       b if sel == 01\n *       c if sel == 10\n *       d if sel == 11\n */\n\nCHIP Mux4Way16 {\n    IN a[16], b[16], c[16], d[16], sel[2];\n    OUT out[16];\n\n    PARTS:\n    Mux16(a=a, b=b, sel=sel[0], out=outab);\n    Mux16(a=c, b=d, sel=sel[0], out=outcd);\n    Mux16(a=outab, b=outcd, sel=sel[1], out=out);\n}\n```\n\n### output file Mux8Way16 gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222692038-abdb9e6c-f659-4161-a1e0-dcb02b50b6bc.png)\n\n### compare file Mux8Way16 gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222692111-3cb90396-42b2-46bb-9811-73b9e91d6fd3.png)\n\n### Mux8Way16 gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/222692666-b7d4c997-7ce1-4f39-bb33-4d5af16b6c7a.png)\n\n## 14. ALU\n\n![RonBurgundyBigDealGIF](https://user-images.githubusercontent.com/91504420/222680020-03ed4ca5-719c-43ce-b5c3-3c5b822b109e.gif)\n\nALU stands for Arithmetic Logic Unit. It is a digital circuit that performs arithmetic and logic operations on binary numbers. The arithmetic operations include addition, subtraction, multiplication, and division. The logic operations include AND, OR, NOT, and XOR.\n\nThe ALU is an essential component of a microprocessor or CPU (Central Processing Unit), where it performs mathematical and logical operations to process instructions and data. It receives input from the processor's registers, performs the necessary operation, and stores the result in a register for later use.\n\nThe ALU's design varies depending on the architecture of the processor, but it typically consists of combinational logic circuits and a set of control circuits to manage the operations. ALUs are typically built with a variety of bit-widths, such as 8-bit, 16-bit, 32-bit, or 64-bit, depending on the processor's design.\n\nOverall, the ALU is a critical component of any digital circuit that performs arithmetic and logic operations on binary numbers, making it an essential part of modern computing.\n\n![image](https://user-images.githubusercontent.com/91504420/222679798-897fa3fb-f16b-4925-88f7-c10921eff527.png)\n\n\n## 15. NUMERAL SYSTEM\n\n![HaveFaithInTheSystemReginaldJuneGIF](https://user-images.githubusercontent.com/91504420/222785705-07ae0b9f-77f8-4e16-864a-bcaf3d2cf6d6.gif)\n\nA numeral system, also known as a number system, is a mathematical notation for representing numbers using digits or symbols. The most commonly used numeral systems are the decimal system (base-10), binary system (base-2), octal system (base-8), and hexadecimal system (base-16).\n\nIn a numeral system, each digit represents a specific value, and the position of the digit determines its place value. For example, in the decimal system, the digit \"3\" represents three ones, while the digit \"3\" in the tens place represents three tens (or 30).\n\nThe binary system is used extensively in computing, where all data is represented in binary form. It uses only two digits (0 and 1) and is the foundation for digital electronics.\n\nThe octal system is commonly used in computer programming, particularly when working with Unix or Linux operating systems, while the hexadecimal system is frequently used in computer programming and digital electronics because it provides a convenient way to represent large binary numbers in a compact form.\n\nOverall, numeral systems are essential to mathematics and computing, as they allow us to represent and manipulate numbers in a systematic and consistent way.\n\n![image](https://user-images.githubusercontent.com/91504420/222683793-05df0eb4-010a-43d4-87a0-daaba967470b.png)\n\n## 16. BINARY NUMBERS\n\n![WeOnlyHaveTwoOnlyTwoGIF](https://user-images.githubusercontent.com/91504420/222825918-ab07621b-89dd-478e-af9f-da1c72cad073.gif)\n\nBinary numbers are a base-2 number system that uses only two digits, 0 and 1, to represent all values. Each digit in a binary number represents a power of two, with the rightmost digit representing 2^0 (or 1), the second rightmost representing 2^1 (or 2), and so on. The number is formed by summing the values of the digits that are set to 1. Binary numbers are commonly used in computing and digital electronics because they can easily be represented as electronic signals, and digital logic can easily manipulate them. Converting between binary and decimal (base-10) numbers involves multiplying or adding the powers of 2 corresponding to the set 1 digits in the binary number.\n\n![image](https://user-images.githubusercontent.com/91504420/222826103-7d109a6b-08df-4ee0-b2e5-8b56730266df.png)\n\n## 17. BINARY ARITHMETIC\n\n![HoodycatHoodycatsGIF](https://user-images.githubusercontent.com/91504420/222828266-23de023c-1d5e-4f3f-be49-b37ccabd4821.gif)\n\nBinary arithmetic is a form of arithmetic that operates on binary numbers, which are numbers represented in the base-2 numeral system. In binary arithmetic, there are only two digits: 0 and 1. Binary arithmetic includes basic mathematical operations such as addition, subtraction, multiplication, and division.\n\nIn binary addition, the rules are similar to decimal addition, except that when the sum of two digits is 2 or greater, a carry-over occurs. For example, in binary addition, 1 + 1 = 10, where the 1 is carried over to the next digit. In binary subtraction, the rules are also similar to decimal subtraction, but borrowing may occur when the digit in the minuend is smaller than the corresponding digit in the subtrahend.\n\nIn binary multiplication, the process is similar to decimal multiplication, but the multiplication table is much simpler since there are only two digits. In binary division, the process is similar to decimal division, but the steps are more complex since there may be multiple digits involved in the dividend and divisor.\n\nBinary arithmetic is used extensively in computer science and digital electronics since digital devices operate using binary signals. The principles of binary arithmetic are also important for understanding concepts such as binary code, digital circuits, and computer programming.\n\n![image](https://user-images.githubusercontent.com/91504420/222828486-92fb81c0-0559-455f-a541-59057aefe144.png)\n\n![image](https://user-images.githubusercontent.com/91504420/222828706-7f103445-173c-49cf-a05b-69357fb6b9bc.png)\n\n![image](https://user-images.githubusercontent.com/91504420/222828987-57a7616d-c97a-4ff7-b2f5-ffc861c11b5d.png)\n\n![image](https://user-images.githubusercontent.com/91504420/222829455-d3f67f5a-7d40-4ef3-8c96-c8c45a824715.png)\n\n## 18. HACK ALU\n\n![WowTheRockGIF](https://user-images.githubusercontent.com/91504420/222835464-b7ff6e8a-cd0f-4ab9-969a-0965498f26dc.gif)\n\nHack ALU (Arithmetic Logic Unit) is a component of the Hack computer, which is a simple computer architecture designed for educational purposes. The ALU is responsible for performing arithmetic and logical operations on binary data.\n\nThe Hack ALU is a 16-bit unit that supports several arithmetic operations, including addition, subtraction, and bitwise logical operations such as AND, OR, and NOT. It also supports some comparison operations such as equal, less than, and greater than.\n\nThe Hack ALU is built using basic logic gates such as AND, OR, and XOR gates, and uses a combination of these gates to perform the various operations. The output of the ALU is a 16-bit value that can be stored in a register or used as input to other components of the computer.\n\nThe Hack computer architecture was designed as a teaching tool to help students learn about computer organization and architecture. The design is simple and easy to understand, making it a good starting point for beginners. The Hack ALU is an important component of the computer and provides a basic understanding of how arithmetic and logical operations are performed in a computer system.\n\n![image](https://user-images.githubusercontent.com/91504420/222835265-e79ec11a-b5f5-4569-b2a0-ba3ca7e090c1.png)\n\n![image](https://user-images.githubusercontent.com/91504420/222835588-f52366dc-c1c7-44ff-afb5-6f1f9f4f41c5.png)\n\n![image](https://user-images.githubusercontent.com/91504420/222836405-b2a21dfc-cb48-4c63-9b24-462c72563d8f.png)\n\n\n## 19. PROJECT2\n\n![ItsJustTooEasyMonétXChangeGIF](https://user-images.githubusercontent.com/91504420/222895932-b4bae7bd-5180-4c99-b95c-dd1f9a9e833d.gif)\n\n## half adder \n\nA half adder is a digital circuit that adds two binary digits (bits) and produces a sum bit and a carry bit as output. It is called a \"half\" adder because it can only add two bits, whereas a full adder can add three bits. The half adder has two inputs, one for each bit being added, and two outputs, one for the sum and one for the carry. The sum output is the result of adding the two input bits together, while the carry output indicates whether there is a carry to the next place value in a multi-digit addition operation. The circuit for a half adder consists of an XOR gate and an AND gate.\n\n![image](https://user-images.githubusercontent.com/91504420/222895953-9b0a3808-d0d9-4a34-95fe-d486397df7c3.png)\n\n### halfAdder logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/02/HalfAdder.hdl\n\n/**\n * Computes the sum of two bits.\n */\n\nCHIP HalfAdder {\n    IN a, b;    // 1-bit inputs\n    OUT sum,    // Right bit of a + b \n        carry;  // Left bit of a + b\n\n    PARTS:\n    Xor(a=a, b=b, out=sum);\n    And(a=a, b=b, out=carry);\n}\n```\n\n### output file halfAdder gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222896101-e36347f5-a458-483d-9bbc-f539d4bc6cbe.png)\n\n### compare file halfAdder gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222896112-cf606bc7-7f51-474c-b674-427571a4cbb7.png)\n\n### halfAdder gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/222896208-0597d4ae-9329-40ee-add3-533c47326f66.png)\n\n## full adder\n\n![ImJustTellingTheTruthCalvinRodneyGIF](https://user-images.githubusercontent.com/91504420/222898117-c787d850-3670-4ca8-b6f2-3fd5b2e4641e.gif)\n\nA full adder is a digital circuit that adds three binary digits (bits) and produces a sum bit and a carry bit as output. It is used to add multi-digit binary numbers by combining multiple full adders to create a ripple carry adder. The full adder has three inputs, one for each of the two bits being added and one for the carry-in from the previous place value, and two outputs, one for the sum and one for the carry-out to the next place value. The circuit for a full adder consists of two XOR gates, two AND gates, and an OR gate. The sum output is the result of adding the three input bits together, while the carry output indicates whether there is a carry to the next place value in a multi-digit addition operation.\n\n\n### fullAdder logic gate solution:\n\n```\n// This file is part of www.nand2tetris.org\n// and the book \"The Elements of Computing Systems\"\n// by Nisan and Schocken, MIT Press.\n// File name: projects/02/FullAdder.hdl\n\n/**\n * Computes the sum of three bits.\n */\n\nCHIP FullAdder {\n    IN a, b, c;  // 1-bit inputs\n    OUT sum,     // Right bit of a + b + c\n        carry;   // Left bit of a + b + c\n\n    PARTS:\n    HalfAdder(a=a, b=b, sum=sumab, carry=carryab);\n    HalfAdder(a=sumab, b=c, sum=sum, carry=carryabc);\n    Or(a=carryab, b=carryabc, out=carry);\n}\n```\n\n### output file fullAdder gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222897796-36ac4b83-42f3-445e-9291-3f1efd4de41b.png)\n\n### compare file fullAdder gate:\n\n![image](https://user-images.githubusercontent.com/91504420/222897807-a496f97b-8637-4e46-a3b7-7b25accb3f28.png)\n\n### fullAdder gate simulation:\n\n![image](https://user-images.githubusercontent.com/91504420/222897676-e644f6f3-e79b-4e18-b1bd-2149f3e71832.png)\n\n\u003c!-- Contact --\u003e\n# :handshake: Contact\n\n\u003cp align=\"left\"\u003e\n\u003ca href=\"https://twitter.com/liron_mizrahi\" target=\"blank\"\u003e\u003cimg align=\"center\" src=\"https://raw.githubusercontent.com/rahuldkjain/github-profile-readme-generator/master/src/images/icons/Social/twitter.svg\" alt=\"liron_mizrahi\" height=\"50\" width=\"60\" /\u003e\u003c/a\u003e\n\u003ca href=\"https://instagram.com/liron.mizrhai1234\" target=\"blank\"\u003e\u003cimg align=\"center\" src=\"https://raw.githubusercontent.com/rahuldkjain/github-profile-readme-generator/master/src/images/icons/Social/instagram.svg\" alt=\"liron.mizrhai1234\" height=\"50\" width=\"60\" /\u003e\u003c/a\u003e\n\u003ca href=\"https://www.linkedin.com/in/%D7%9C%D7%99%D7%A8%D7%95%D7%9F-%D7%9E%D7%96%D7%A8%D7%97%D7%99-1050b421a/\"\u003e\n  \u003cimg align=\"left\" alt=\"liron LinkedIN\" height=\"50\" width=\"60\" src=\"https://raw.githubusercontent.com/peterthehan/peterthehan/master/assets/linkedin.svg\" /\u003e\n\u003c/a\u003e\n\u003c/p\u003e\n\n\u003cp align=\"right\"\u003e(\u003ca href=\"#readme-top\"\u003eback to top\u003c/a\u003e)\u003c/p\u003e\n\n\u003c!-- Acknowledgements --\u003e\n# :gem: Acknowledgements\n\nLinks to information that helped me during construction and learning:\n - [python3](https://docs.python.org/3/)\n - [BeautifulSoup](https://www.crummy.com/software/BeautifulSoup/bs4/doc/)\n\u003cp align=\"right\"\u003e(\u003ca href=\"#readme-top\"\u003eback to top\u003c/a\u003e)\u003c/p\u003e\n\n\u003c!-- About the authors --\u003e\n## :telephone: About the authors\n\n - Liron Mizarhi - Navy soldier and programmer\n\n\u003cp align=\"right\"\u003e(\u003ca href=\"#readme-top\"\u003eback to top\u003c/a\u003e)\u003c/p\u003e\n\n\u003c!-- Project status --\u003e\n## :octocat: Project Status\n\n### Project is: In Progress!\n\n\u003cp align=\"right\"\u003e(\u003ca href=\"#readme-top\"\u003eback to top\u003c/a\u003e)\u003c/p\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flironmiz%2Fnand2tetriscourse","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Flironmiz%2Fnand2tetriscourse","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flironmiz%2Fnand2tetriscourse/lists"}