{"id":13958919,"url":"https://github.com/liuqdev/8-bits-RISC-CPU-Verilog","last_synced_at":"2025-07-21T00:32:37.533Z","repository":{"id":59279332,"uuid":"166614783","full_name":"liuqdev/8-bits-RISC-CPU-Verilog","owner":"liuqdev","description":"Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。","archived":false,"fork":false,"pushed_at":"2019-01-20T02:49:20.000Z","size":7421,"stargazers_count":135,"open_issues_count":2,"forks_count":42,"subscribers_count":3,"default_branch":"master","last_synced_at":"2024-11-28T02:35:39.020Z","etag":null,"topics":["cpu","fsm","risc","verilog"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/liuqdev.png","metadata":{"files":{"readme":"readme.rst","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2019-01-20T02:20:17.000Z","updated_at":"2024-11-18T16:12:08.000Z","dependencies_parsed_at":"2022-09-15T12:30:21.309Z","dependency_job_id":null,"html_url":"https://github.com/liuqdev/8-bits-RISC-CPU-Verilog","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/liuqdev/8-bits-RISC-CPU-Verilog","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/liuqdev%2F8-bits-RISC-CPU-Verilog","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/liuqdev%2F8-bits-RISC-CPU-Verilog/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/liuqdev%2F8-bits-RISC-CPU-Verilog/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/liuqdev%2F8-bits-RISC-CPU-Verilog/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/liuqdev","download_url":"https://codeload.github.com/liuqdev/8-bits-RISC-CPU-Verilog/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/liuqdev%2F8-bits-RISC-CPU-Verilog/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":266221321,"owners_count":23894966,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpu","fsm","risc","verilog"],"created_at":"2024-08-08T13:02:06.633Z","updated_at":"2025-07-21T00:32:32.525Z","avatar_url":"https://github.com/liuqdev.png","language":"Verilog","funding_links":[],"categories":["CPU RISC-V"],"sub_categories":["网络服务_其他"],"readme":null,"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fliuqdev%2F8-bits-RISC-CPU-Verilog","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fliuqdev%2F8-bits-RISC-CPU-Verilog","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fliuqdev%2F8-bits-RISC-CPU-Verilog/lists"}