{"id":13537208,"url":"https://github.com/lmco/axi4_aib_bridge","last_synced_at":"2025-04-02T04:30:25.587Z","repository":{"id":150554597,"uuid":"179549941","full_name":"lmco/axi4_aib_bridge","owner":"lmco","description":"AXI4/AIB Bridge RTL","archived":false,"fork":false,"pushed_at":"2019-05-22T16:32:18.000Z","size":925,"stargazers_count":7,"open_issues_count":0,"forks_count":3,"subscribers_count":5,"default_branch":"master","last_synced_at":"2024-11-03T02:32:38.728Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/lmco.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2019-04-04T18:02:28.000Z","updated_at":"2024-09-30T18:02:30.000Z","dependencies_parsed_at":null,"dependency_job_id":"e51c616a-a622-441a-b3b9-22ed72385c07","html_url":"https://github.com/lmco/axi4_aib_bridge","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lmco%2Faxi4_aib_bridge","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lmco%2Faxi4_aib_bridge/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lmco%2Faxi4_aib_bridge/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lmco%2Faxi4_aib_bridge/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/lmco","download_url":"https://codeload.github.com/lmco/axi4_aib_bridge/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246756742,"owners_count":20828756,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-01T09:00:56.319Z","updated_at":"2025-04-02T04:30:24.606Z","avatar_url":"https://github.com/lmco.png","language":"SystemVerilog","funding_links":[],"categories":["Connectivity","AIB"],"sub_categories":[],"readme":"[1]: https://github.com/lmco/tlrb_aib_phy\n[2]: https://www.intel.com/content/www/us/en/architecture-and-technology/programmable/heterogeneous-integration/overview.html\n\n# axi4_aib_bridge\n\nThis project builds on the Advanced Interface Bus (AIB) by adding a protocol bridge to convert Advanced\nMicrocontroller Bus Architecture (AMBA) Advanced eXtensible Interface 4 (AXI4) to AIB and vice versa. To achieve this,\nAXI4 is converted to the lightweight Chiplet Protocol Interface (CPI) which is then directly mapped to AIB. The AXI4/AIB\nBridge enables the extension of the standard AXI4 interface across physically separate chiplets by leveraging AIB.\nConverting AXI4 to AIB allows for a standard, low-power, low-latency, parallel chip-to-chip interface while maintaining\na high pin efficiency and at a minimal performance impact.\n\nThe AIB Register-Transfer Level (RTL) used in this project is leveraged from [tlrb_aib_phy][1]. To validate compliance\nwith AXI4, New Wave Design and Verification performed the functional test and simulation of the design and their full\nreport can be found in the 'doc' directory.\n\nMore information on the AIB and its specification can be found on Intel's website [here][2].\n\n## Cloning\n\nSince this repository uses git submodules, it's recommended to use the --recurse-submodules flag when cloning:\n```\ngit clone --recurse-submodules https://github.com/lmco/axi4_aib_bridge.git\n```\n\nOtherwise the submodules can be pulled in to an already cloned repository by running the following git command:\n```\ngit submodule update --init --recursive\n```\n\n## Dependencies\n\n* [tlrb_aib_phy][1]\n\nThis project also requires the AXI4/CPI Bridge RTL source code from Micron to compile and run. Please contact Micron to \nrequest a copy of that code.\n\n## Directory Structure\n\n```\n.\n|   LICENSE                                             # License file\n|   README.md                                           # This file\n|   \n+---doc                                                 # Documentation\n|       DARPA_CHIPS_FinalTestAndIntegrationReport.pdf   # Test \u0026 Integration Report for AXI4/AIB Bridge\n|       \n+---lib                                                 # Submodules\n|   \\---tlrb_aib_phy\n|                   \n\\---rtl                                                 # AXI4/AIB Bridge source files\n        axim_cpi_aib_aib_cpi_axis.v\n        master_cpi_aib.sv\n        slave_cpi_aib.sv\n```\n\n## Authors\n\n* Lockheed Martin Corporation\n* New Wave Design and Verification\n\n## License\n\nThis project is licensed under the Apache 2.0 License - see the LICENSE file for more details\n\n## Distribution Statement\n\nDISTRIBUTION STATEMENT A. Approved for public release.\n\nThe views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the\nofficial views or policies of the Department of Defense or the U.S. Government.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flmco%2Faxi4_aib_bridge","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Flmco%2Faxi4_aib_bridge","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flmco%2Faxi4_aib_bridge/lists"}