{"id":20981962,"url":"https://github.com/lowrisc/gsoc-sim-mem","last_synced_at":"2026-03-14T18:37:16.850Z","repository":{"id":52786749,"uuid":"268489401","full_name":"lowRISC/gsoc-sim-mem","owner":"lowRISC","description":"A simulated memory controller for use in FPGA designs that want to model real system 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gsoc-sim-mem\n\nA simulated memory controller for use in FPGA designs that want to model real system performance.\n\nThis project has been developed in the Google Summer of Code 2020 for [LowRisc CIC](https://www.lowrisc.org/), supervised by [Greg Chadwick](https://github.com/GregAC), [Pirmin Vogel](https://github.com/vogelpi) and [Alex Bradbury](https://github.com/asb).\n\n![Overview](https://i.imgur.com/BwElPLe.png)\n\n## How to contribute\n\nHave a look at [CONTRIBUTING](./CONTRIBUTING.md) for guidelines on how to contribute code to this repository.\n\n## Licensing\n\nUnless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see [LICENSE](./LICENSE) for full text).\n\n## How to use\n\nThe simulated memory controller has two AXI ports (one slave and one master) dedicated to its integration between the requester (typically the CPU core) and the real memory controller.\n\nTwo testbenches are integrated in the repository:\n\n- A testbench for the whole simulated memory controller, which is discussed here.\n- A testbench for the response banks, as it is a relatively complex design block.\n\nSee the [documentation](https://github.com/lowrisc/gsoc-sim-mem/documentation.md) for more information about the testbenches.\n\nThe required tools are [Verilator](https://www.veripool.org/wiki/verilator) and [FuseSoC](https://github.com/olofk/fusesoc).\nAdditionally, [GTKWave](http://gtkwave.sourceforge.net/) is used for analyzing waveforms.\n\n### Initial setup\n\nTo run the complete testbench,\n\n**Step 1:** Clone the repository and move to the repository root:\n\n```bash\ngit clone https://github.com/lowRISC/gsoc-sim-mem.git simmem\ncd simmem\n```\n\n**Step 2:** Initialize FuseSoC and add the simmem core:\n\n```bash\nfusesoc init\nfusesoc library add simmem .\n```\n\n### Testbench execution\n\nThe main testbench checks the functionality and performance of the simulated memory controller by:\n\n- Checking the write response ordering according to the corresponding requests.\n- Displaying the actual delays.\n\n**Step 1:** To compile the design and testbench, execute:\n\n```bash\nfusesoc run --target=sim_simmem_top simmem\n```\n\n**Step 2:** To generate the waveforms, execute:\n\n```bash\n./build/simmem_0.1/sim_simmem_top-verilator/Vsimmem_top --trace\n```\n\nThis runs the testbench again, but this time it generates the `top.fst` wave file.\nThe testbench standard output is described in the [documentation](https://github.com/lowrisc/gsoc-sim-mem/documentation.md).\n\n**Step 3:** To view the waveforms, execute:\n\n```bash\ngtkwave top.fst\n```\n\nThis opens the waveform GUI for a deeper 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