{"id":20981963,"url":"https://github.com/lowrisc/ibex","last_synced_at":"2026-01-27T17:36:12.401Z","repository":{"id":38419218,"uuid":"99689233","full_name":"lowRISC/ibex","owner":"lowRISC","description":"Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.","archived":false,"fork":false,"pushed_at":"2024-12-06T15:13:21.000Z","size":40632,"stargazers_count":1400,"open_issues_count":210,"forks_count":548,"subscribers_count":98,"default_branch":"master","last_synced_at":"2024-12-06T21:30:57.921Z","etag":null,"topics":["cpucore","hardware","risc-v","rv32"],"latest_commit_sha":null,"homepage":"https://www.lowrisc.org","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/lowRISC.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":"SECURITY.md","support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2017-08-08T12:16:36.000Z","updated_at":"2024-12-06T15:13:23.000Z","dependencies_parsed_at":"2024-03-07T16:47:44.860Z","dependency_job_id":"c1f37648-c49d-45e2-a167-b85c0fe9d55f","html_url":"https://github.com/lowRISC/ibex","commit_stats":null,"previous_names":["pulp-platform/zero-riscy"],"tags_count":8,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lowRISC%2Fibex","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lowRISC%2Fibex/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lowRISC%2Fibex/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lowRISC%2Fibex/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/lowRISC","download_url":"https://codeload.github.com/lowRISC/ibex/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243384239,"owners_count":20282316,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpucore","hardware","risc-v","rv32"],"created_at":"2024-11-19T05:42:02.718Z","updated_at":"2026-01-27T17:36:12.345Z","avatar_url":"https://github.com/lowRISC.png","language":"SystemVerilog","readme":"[Ibex OpenTitan configuration Nightly Regression](https://ibex.reports.lowrisc.org/opentitan/latest/report.html)\n\u003ca href=\"https://ibex.reports.lowrisc.org/opentitan/latest/report.html\"\u003e\n  \u003cimg src=\"https://ibex.reports.lowrisc.org/opentitan/latest/summary.svg\"\u003e\n\u003c/a\u003e\n\n# Ibex RISC-V Core\n\nIbex is a production-quality open source 32-bit RISC-V CPU core written in\nSystemVerilog. The CPU core is heavily parametrizable and well suited for\nembedded control applications. Ibex is being extensively verified and has\nseen multiple tape-outs. Ibex supports the Integer (I) or Embedded (E),\nInteger Multiplication and Division (M), Compressed (C), and B (Bit\nManipulation) extensions.\n\n\u003cp align=\"center\"\u003e\u003cimg src=\"doc/03_reference/images/blockdiagram.svg\" width=\"650\"\u003e\u003c/p\u003e\n\nIbex was initially developed as part of the [PULP platform](https://www.pulp-platform.org)\nunder the name [\"Zero-riscy\"](https://doi.org/10.1109/PATMOS.2017.8106976), and has been\ncontributed to [lowRISC](https://www.lowrisc.org) who maintains it and develops it further. It is\nunder active development.\n\n## Configuration\n\nIbex offers several configuration parameters to meet the needs of various application scenarios.\nThe options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features.\nThe table below indicates performance, area and verification status for a few selected configurations.\nThese are configurations on which lowRISC is focusing for performance evaluation and design verification (see [supported configs](ibex_configs.yaml)).\n\n| Config | \"micro\" | \"small\" | \"maxperf\" | \"maxperf-pmp-bmfull\" |\n| ------ | ------- | --------| ----------| -------------------- |\n| Features | RV32EC | RV32IMC, 3 cycle mult | RV32IMC, 1 cycle mult, Branch target ALU, Writeback stage | RV32IMCB, 1 cycle mult, Branch target ALU, Writeback stage, 16 PMP regions |\n| Performance (CoreMark/MHz) | 0.904 | 2.47 | 3.13 | 3.13 |\n| Area - Yosys (kGE) | 16.85 | 26.60 | 32.48 | 66.02 |\n| Area - Commercial (estimated kGE) | ~15 | ~24 | ~30 | ~61 |\n| Verification status | Red | Green | Green | Green |\n\nNotes:\n\n* Performance numbers are based on CoreMark running on the Ibex Simple System [platform](examples/simple_system/README.md).\n  Note that different ISAs (use of B and C extensions) give the best results for different configurations.\n  See the [Benchmarks README](examples/sw/benchmarks/README.md) for more information.\n* Yosys synthesis area numbers are based on the Ibex basic synthesis [flow](syn/README.md) using the latch-based register file.\n* Commercial synthesis area numbers are a rough estimate of what might be achievable with a commercial synthesis flow and technology library.\n* For comparison, the original \"Zero-riscy\" core yields an area of 23.14kGE using our Yosys synthesis flow.\n* Verification status is a rough guide to the overall maturity of a particular configuration.\n  Green indicates that verification is close to complete.\n  Amber indicates that some verification has been performed, but the configuration is still experimental.\n  Red indicates a configuration with minimal/no verification.\n  Users must make their own assessment of verification readiness for any tapeout.\n* v.1.0.0 of the RISC-V Bit-Manipulation Extension is supported as well as the remaining sub-extensions of draft v.0.93 of the bitmanip spec.\n  The latter are *not ratified* and there may be changes before ratification.\n  See [Standards Compliance](https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html) in the Ibex documentation for more information.\n\n## Documentation\n\nThe Ibex user manual can be\n[read online at ReadTheDocs](https://ibex-core.readthedocs.io/en/latest/). It is also contained in\nthe `doc` folder of this repository.\n\n## Examples\n\nThe Ibex repository includes [Simple System](examples/simple_system/README.md).\nThis is an intentionally simple integration of Ibex with a basic system that targets simulation.\nIt is intended to provide an easy way to get bare metal binaries running on Ibex in simulation.\n\nA more complete example can be found in the [Ibex Demo System repository](https://github.com/lowrisc/ibex-demo-system).\nIn particular it includes a integration of the [PULP RISC-V debug module](https://github.com/pulp-platform/riscv-dbg).\nIt targets the [Arty A7 FPGA board from Digilent](https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/) and supports debugging via OpenOCD and GDB over USB (no external JTAG probe required).\nThe Ibex Demo System is maintained by lowRISC but is not an official part of Ibex.\n\n## Contributing\n\nWe highly appreciate community contributions. To ease our work of reviewing your contributions,\nplease:\n\n* Create your own branch to commit your changes and then open a Pull Request.\n* Split large contributions into smaller commits addressing individual changes or bug fixes. Do not\n  mix unrelated changes into the same commit!\n* Write meaningful commit messages. For more information, please check out the [contribution\n  guide](https://github.com/lowrisc/ibex/blob/master/CONTRIBUTING.md).\n* If asked to modify your changes, do fixup your commits and rebase your branch to maintain a\n  clean history.\n\nWhen contributing SystemVerilog source code, please try to be consistent and adhere to [our Verilog\ncoding style guide](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md).\n\nWhen contributing C or C++ source code, please try to adhere to [the OpenTitan C++ coding style\nguide](https://opentitan.org/book/doc/contributing/style_guides/c_cpp_coding_style.html).\nAll C and C++ code should be formatted with clang-format before committing.\nEither run `clang-format -i filename.cc` or `git clang-format` on added files.\n\nTo get started, please check out the [\"Good First Issue\"\n list](https://github.com/lowrisc/ibex/issues?q=is%3Aissue+is%3Aopen+label%3A%22Good+First+Issue%22).\n\n## Issues and Troubleshooting\n\nIf you find any problems or issues with Ibex or the documentation, please check out the [issue\n tracker](https://github.com/lowrisc/ibex/issues) and create a new issue if your problem is\nnot yet tracked.\n\n## Questions?\n\nDo not hesitate to contact us, e.g., on our public [Ibex channel on\nZulip](https://lowrisc.zulipchat.com/#narrow/stream/198227-ibex)!\n\n## License\n\nUnless otherwise noted, everything in this repository is covered by the Apache\nLicense, Version 2.0 (see LICENSE for full text).\n\n## Credits\n\nMany people have contributed to Ibex through the years. Please have a look at\nthe [credits file](CREDITS.md) and the commit history for more information.\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flowrisc%2Fibex","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Flowrisc%2Fibex","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flowrisc%2Fibex/lists"}