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Tiny RISC-V CPU\n\u003e An implementation of RV32I ISA\n\n## 描述\n\n一个简单的 RV32I 指令集 CPU，带有冲突检测和前递功能，包含单周期和五阶段流水线的版本。\n\n## 支持的指令\n\n这个 CPU 支持的指令是 RV32I 的一个**真子集**\n\n- 访存指令: sb, sh, sw, lb, lh, lw, lbu, lhu\n- 整数运算指令: add, sub, xor, or, and, srl, sra, sll\n- 逻辑指令: xori, ori, andi, srli, srai, slli\n- 整数比较指令: slt, sltu, slti, sltiu\n- 跳转指令: jal, jalr\n- 分支指令: beq, bne, blt, bge, bltu, bgeu\n\n## 运行方法\n\n### 准备工作\n\n根据实际情况修改 `defines.v` 文件的以下参数：\n\n- `DEBUG`：启用调试模式（会在 ModelSim 或者 Vivado 的仿真控制台输出调试信息）\n- `PIPELINING`：选择流水线版本\n- `FPGA`：提供 Nexys4-DDR 支持\n- `IMEM_SIZE` 和 `IMEM_SIZE_WIDTH`：指令内存的大小和地址位宽\n- `DMEM_SIZE` 和 `DMEM_SIZE_WIDTH`：数据内存的大小和地址位宽\n\n### ModelSim 仿真\n\n1. 将项目根目录中所有.v文件导入到 ModelSim 中；\n\n2. 注释 `defines.v` 文件中的 ``define FPGA`；\n\n3. 将 `teshbench.v` 文件中的以下代码改为希望执行的 RISC-V 机器码程序文件（可从tests文件夹获取，需添加到 ModelSim 项目中）\n\n   ```verilog\n   $readmemh(\"riscv32_sim1.dat\", cpu.imem.RAM);\n   ```\n\n4. 编译后即可选择顶层文件 `testbench` 进行仿真。\n\n### FPGA\n\n\u003e 本仓库仅提供在 Nexys4-DDR 开发平台上运行的约束文件，如需使用其他开发平台，请根据开发平台提供商提供的文档进行修改。\n\n1. 切换到 Nexys4DDR 分支；\n2. 在 Vivado 中打开此项目；\n3. 修改初始化 IMEM 的 coe 文件来更改希望运行的程序；\n4. 依次执行综合、实现、生成比特流后即可下载到 Nexys4-DDR 开发平台。\n\n本仓库默认的 coe 文件是一个冒泡排序程序，各个开关的含义和具体的使用方法请参考 tests/FPGA/riscv-studentnosorting.asm\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flsx-s-software%2Ftiny-riscv-cpu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Flsx-s-software%2Ftiny-riscv-cpu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flsx-s-software%2Ftiny-riscv-cpu/lists"}