{"id":21712088,"url":"https://github.com/ltcmelo/y86proc","last_synced_at":"2026-01-30T03:50:17.305Z","repository":{"id":24067431,"uuid":"27453703","full_name":"ltcmelo/Y86Proc","owner":"ltcmelo","description":"Y86 Processor implementation for the Altera DE2-115 FPGA","archived":false,"fork":false,"pushed_at":"2015-01-23T01:40:10.000Z","size":160,"stargazers_count":5,"open_issues_count":0,"forks_count":2,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-06-08T06:08:31.000Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ltcmelo.png","metadata":{"files":{"readme":"README","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2014-12-02T21:12:31.000Z","updated_at":"2025-04-05T18:40:46.000Z","dependencies_parsed_at":"2022-08-22T10:40:18.993Z","dependency_job_id":null,"html_url":"https://github.com/ltcmelo/Y86Proc","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ltcmelo/Y86Proc","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ltcmelo%2FY86Proc","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ltcmelo%2FY86Proc/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ltcmelo%2FY86Proc/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ltcmelo%2FY86Proc/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ltcmelo","download_url":"https://codeload.github.com/ltcmelo/Y86Proc/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ltcmelo%2FY86Proc/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28900243,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-30T03:36:35.398Z","status":"ssl_error","status_checked_at":"2026-01-30T03:36:34.949Z","response_time":66,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-25T23:33:40.310Z","updated_at":"2026-01-30T03:50:17.291Z","avatar_url":"https://github.com/ltcmelo.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"Y86 Processor Implementation for the Altera DE2-115\n\nThe original version of this code comes from the book \"Computer Systems: A\nProgrammer's Perspective (2o. Edition)\", which is copyrighted by the authors\nRandal E. Bryant and David R O'Hallaron.\n\nThe adaptation for the Altera DE2-115 FPGA along with further extensions\nare authored by Leandro T. C. Melo with contributions by Jeferson Chaves.\nNo warranties of any kind given.\n\nThe overall design of the processor is pretty much the same. However, the\nFetch and Memory stages needed to be completely re-written and a few other\nparts adjusted. This is because the SRAM component from the DE2-115 do not\nsatisfy the requirements of the original implementation, which are too\nstrong: It assumes a memory component with 8 banks, no alignment\nrestrictions, possibility of simultaneous read of instructions and data,\nand the ability to entirely fetch the 48 bits of maximum instruction\nlength at once.\n\nyas - There is a patch available that generates Verilog code in the format\nrequired by the DE2-115 board and the extensions I implemented. Notice,\nhowever, that the simulator might no longer work once the patch is applied,\nsince I did not bother about that and was only interested on the assembler.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fltcmelo%2Fy86proc","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fltcmelo%2Fy86proc","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fltcmelo%2Fy86proc/lists"}