{"id":13444318,"url":"https://github.com/lvyufeng/step_into_mips","last_synced_at":"2026-03-09T16:53:05.778Z","repository":{"id":37388995,"uuid":"118303050","full_name":"lvyufeng/step_into_mips","owner":"lvyufeng","description":"一步一步写MIPS CPU","archived":false,"fork":false,"pushed_at":"2021-08-04T13:31:16.000Z","size":35863,"stargazers_count":785,"open_issues_count":2,"forks_count":157,"subscribers_count":17,"default_branch":"master","last_synced_at":"2025-03-20T18:41:31.652Z","etag":null,"topics":["mips-cpu","nscscc","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/lvyufeng.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2018-01-21T04:05:44.000Z","updated_at":"2025-03-19T08:37:40.000Z","dependencies_parsed_at":"2022-09-15T00:11:14.311Z","dependency_job_id":null,"html_url":"https://github.com/lvyufeng/step_into_mips","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/lvyufeng/step_into_mips","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lvyufeng%2Fstep_into_mips","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lvyufeng%2Fstep_into_mips/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lvyufeng%2Fstep_into_mips/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lvyufeng%2Fstep_into_mips/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/lvyufeng","download_url":"https://codeload.github.com/lvyufeng/step_into_mips/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lvyufeng%2Fstep_into_mips/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30303113,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-09T14:33:48.460Z","status":"ssl_error","status_checked_at":"2026-03-09T14:33:48.027Z","response_time":61,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["mips-cpu","nscscc","verilog"],"created_at":"2024-07-31T03:02:24.617Z","updated_at":"2026-03-09T16:53:05.770Z","avatar_url":"https://github.com/lvyufeng.png","language":"Verilog","funding_links":[],"categories":["Verilog","CPU RISC-V"],"sub_categories":["网络服务_其他"],"readme":"## 计算机组成原理实验与参考实现\n\n本仓库包含重庆大学由2017年开始实施的计算机组成原理课程改革实验内容，通过合理的梯度划分，一步一步由单独器件连接构成CPU，最后实现一个简单的MIPS五级流水CPU。\n\n本项目实验为《硬件综合设计》课程前导，同时也可作为NSCSCC（龙芯杯系统能力培养大赛）的入门教程。\n\n****\n课程共有四次实验，分别为：\n1. ALU设计，存储器IP使用: [lab_1](https://github.com/cquca/step_into_mips/tree/lab_1)\n2. 简单的取指译码模块: [lab_2](https://github.com/cquca/step_into_mips/tree/lab_2)\n3. 单周期MIPS CPU设计: [lab_3](https://github.com/cquca/step_into_mips/tree/lab_3)\n4. 简单五级流水线MIPS CPU设计: [lab_4](https://github.com/cquca/step_into_mips/tree/lab_4)\n\n相关文档资料和分别于本仓库不同分支。\n\n预备知识和器件实现:[prepare](https://github.com/cquca/step_into_mips/tree/prepare)\n\n附录文档:[appendix](https://github.com/cquca/step_into_mips/tree/appendix)\n****\n**参考与致谢**\n\n本实验内容以《Digital Design and Computer Architecture》为依托进行设计，同时引入了大量由龙芯中科提供的比赛资源，作为参考文档，特此感谢。\n\n若有参考需求，请访问：\n\n**DDCA:** [Elsevier Book Store](https://www.elsevier.com/books/digital-design-and-computer-architecture/harris/978-0-12-394424-5)\n\n**NSCSCC:** [全国大学生系统能力培养大赛官网](http://www.nscscc.org/)\n\n****","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flvyufeng%2Fstep_into_mips","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Flvyufeng%2Fstep_into_mips","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flvyufeng%2Fstep_into_mips/lists"}