{"id":17321290,"url":"https://github.com/m13253/sbmips","last_synced_at":"2026-02-12T01:38:57.986Z","repository":{"id":147642958,"uuid":"92018771","full_name":"m13253/sbmips","owner":"m13253","description":"Naïve MIPS32-like CPU design with pipeline on a Xilinx FPGA","archived":false,"fork":false,"pushed_at":"2017-05-24T09:12:49.000Z","size":37,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-08-20T22:36:32.062Z","etag":null,"topics":["fpga","mips","mips32","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/m13253.png","metadata":{"files":{"readme":"Readme.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2017-05-22T06:26:24.000Z","updated_at":"2025-04-12T02:53:35.000Z","dependencies_parsed_at":null,"dependency_job_id":"baf72354-b1bf-424f-a865-1daf3c72a6cf","html_url":"https://github.com/m13253/sbmips","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/m13253/sbmips","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/m13253%2Fsbmips","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/m13253%2Fsbmips/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/m13253%2Fsbmips/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/m13253%2Fsbmips/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/m13253","download_url":"https://codeload.github.com/m13253/sbmips/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/m13253%2Fsbmips/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29352955,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-12T01:03:07.613Z","status":"ssl_error","status_checked_at":"2026-02-12T01:00:51.346Z","response_time":97,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","mips","mips32","verilog"],"created_at":"2024-10-15T13:36:19.653Z","updated_at":"2026-02-12T01:38:57.968Z","avatar_url":"https://github.com/m13253.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# sbmips\n\nNaïve MIPS32-like CPU design on a Xilinx FPGA\n\n## Features\n\n- Five-stage pipeline\n- Data forwarding\n- One-instruction delay slot\n\n- No branch prediction\n- No privileged instructions\n- No interruptions or exceptions\n\nAcademic reference purpose only, contains bugs, not suitable for production.\n\n## Implemented instructions\n\n### R-Type\n\n- `sll` - Logical left shift\n- `srl` - Logical right shift\n- `sra` - Arithmetical right shift\n- `sllv` - Logical left shift by value\n- `srlv` - Logical right shift by value\n- `srav` - Arithmetical right shift by value\n- `jr` - Jump by register\n- `jalr` - Jump and link by register\n- `add` - Add\n- `addu` - Add without overflow check\n- `sub` - Subtract\n- `subu` - Subtract without overflow check\n- `and` - Bitwise and\n- `or` - Bitwise or\n- `xor` - Bitwise exclusive or\n- `nor` - Bitwise not or\n- `slt` - Set if less than\n- `sltu` - Set if unsigned less than\n\n### I-Type\n\n- `beq` - Branch if equal\n- `bne` - Branch if not equal\n- `addi` - Add immediate value\n- `addiu` - Add immediate value without overflow check\n- `slti` - Set if less than immediate value\n- `sltiu` - Set if less than unsigned immediate value\n- `andi` - Bitwise and immediate value\n- `ori` - Bitwise or immediate value\n- `xori` - Bitwise exclusive or immediate value\n- `lui` - Load immediate value as upper half-word\n- `lw` - Load word from memory\n- `sw` - Store word from memory\n\n### J-Type\n\n- `j` - Jump\n- `jal` - Jump and link\n\n### Available pseudo-instructions\n\n- `la` - Load address\n- `li` - Load immediate value\n- `move` - Move register\n- `negu` - Negation\n- `nop` - No operation\n- `not` - Bitwise not\n- `b` - Branch\n- `bal` - Branch and link\n- `beqz` - Branch if equal to zero\n- `bnez` - Branch if not equal to zero\n\n## Model\n\nDevelopment board: Digilent Nexys 3\n\nFPGA chip: Xilinx Spartan-6 `xc6slx16-3csg324`\n\n## I/O\n\n- `clk (btn)` and `rst` are controlled by two buttons, so you can single-step over the program.\n\n- `gclk` is driven by 100 MHz quartz crystal resonator.\n\n- `led_sel` is bond to 8 switches.\n\n- `led` powers the 4-digit seven-segmented display, showing values of different registers according to `led_sel`.\n\n## License\n\nReleased under GNU General Public License version 3 (GPLv3).\n\nSee [LICENSE](LICENSE) for more information.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fm13253%2Fsbmips","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fm13253%2Fsbmips","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fm13253%2Fsbmips/lists"}