{"id":22007453,"url":"https://github.com/marekpikula/quartus-sv-gotchas","last_synced_at":"2026-03-19T21:30:36.224Z","repository":{"id":83837662,"uuid":"209272731","full_name":"MarekPikula/quartus-sv-gotchas","owner":"MarekPikula","description":"Document describing different gotchas in Intel Quartus SystemVerilog code synthesis.","archived":false,"fork":false,"pushed_at":"2019-10-21T09:53:17.000Z","size":29,"stargazers_count":2,"open_issues_count":1,"forks_count":1,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-10-09T08:23:01.252Z","etag":null,"topics":["quartus","rtl","systemverilog"],"latest_commit_sha":null,"homepage":null,"language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"cc-by-4.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/MarekPikula.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-09-18T09:42:34.000Z","updated_at":"2025-02-22T23:45:34.000Z","dependencies_parsed_at":"2023-03-10T10:45:17.212Z","dependency_job_id":null,"html_url":"https://github.com/MarekPikula/quartus-sv-gotchas","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/MarekPikula/quartus-sv-gotchas","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MarekPikula%2Fquartus-sv-gotchas","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MarekPikula%2Fquartus-sv-gotchas/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MarekPikula%2Fquartus-sv-gotchas/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MarekPikula%2Fquartus-sv-gotchas/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/MarekPikula","download_url":"https://codeload.github.com/MarekPikula/quartus-sv-gotchas/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MarekPikula%2Fquartus-sv-gotchas/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29502928,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-16T05:57:17.024Z","status":"ssl_error","status_checked_at":"2026-02-16T05:56:49.929Z","response_time":115,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["quartus","rtl","systemverilog"],"created_at":"2024-11-30T01:26:54.869Z","updated_at":"2026-02-16T07:01:21.310Z","avatar_url":"https://github.com/MarekPikula.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"# Intel Quartus SystemVerilog gotchas\n\nIn this document I would like to express my discontent with Intel Quartus SystemVerilog support and ways to work around the gotchas I stumbled upon, while porting [PULPissimo](https://github.com/pulp-platform/pulpissimo/) SoC system to Quartus.\n\nThe document is currently work in progress since the porting isn't finished yet, but the author wanted to make a catalog of all the little things he stumbled upon for future reference, while working on the code.\n\nYou can find it in [Intel Quartus SystemVerilog gotchas](Intel Quartus SystemVerilog gotchas.md) document.\n\nAll documents in this repository are licensed under Creative Commons Attribution 4.0 International ([CC-BY 4.0](https://creativecommons.org/licenses/by/4.0/deed)). A copy of the license is in [LICENSE](LICENSE.md) file.\n\nYou can find GitHub pages version [here](https://marekpikula.github.io/quartus-sv-gotchas/).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmarekpikula%2Fquartus-sv-gotchas","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmarekpikula%2Fquartus-sv-gotchas","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmarekpikula%2Fquartus-sv-gotchas/lists"}