{"id":17429778,"url":"https://github.com/marph91/yaaes","last_synced_at":"2025-04-16T02:19:57.694Z","repository":{"id":48075864,"uuid":"233375961","full_name":"marph91/yaaes","owner":"marph91","description":"Yet Another AES implementation in hardware.","archived":false,"fork":false,"pushed_at":"2021-08-08T17:11:07.000Z","size":191,"stargazers_count":7,"open_issues_count":1,"forks_count":1,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-03-29T04:05:06.338Z","etag":null,"topics":["aes","cryptography","fpga","hardware","python","vhdl"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"lgpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/marph91.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-01-12T10:40:34.000Z","updated_at":"2022-08-15T11:28:19.000Z","dependencies_parsed_at":"2022-08-12T18:01:18.847Z","dependency_job_id":null,"html_url":"https://github.com/marph91/yaaes","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/marph91%2Fyaaes","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/marph91%2Fyaaes/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/marph91%2Fyaaes/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/marph91%2Fyaaes/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/marph91","download_url":"https://codeload.github.com/marph91/yaaes/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":249183571,"owners_count":21226222,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["aes","cryptography","fpga","hardware","python","vhdl"],"created_at":"2024-10-17T07:08:56.541Z","updated_at":"2025-04-16T02:19:57.678Z","avatar_url":"https://github.com/marph91.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# YAAES\n\n[![testsuite](https://github.com/marph91/yaaes/workflows/testsuite/badge.svg)](https://github.com/marph91/yaaes/actions?query=workflow%3Atestsuite)\n[![codecov](https://codecov.io/gh/marph91/yaaes/branch/master/graph/badge.svg)](https://codecov.io/gh/marph91/yaaes)\n[![vhdl_style](https://github.com/marph91/yaaes/workflows/vhdl_style/badge.svg)](https://github.com/marph91/yaaes/actions?query=workflow%3Avhdl_style)\n[![synthesis](https://github.com/marph91/yaaes/actions/workflows/synthesis.yml/badge.svg)](https://github.com/marph91/yaaes/actions/workflows/synthesis.yml)\n\nVHDL implementation of the symmetric block cipher AES, as specified in the [NIST FIPS 197](https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.197.pdf), respectively [NIST SP 800-38A](https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38a.pdf).\n\nFeatures:\n\n- Interface width of 8, 32 and 128 bit.\n- Key width of 128 and 256 bit, i. e. AES-128 and AES-256.\n- The following modes:\n\n| Mode | Encryption | Decryption |\n| :---: | :---: | :---: |\n| ECB | :heavy_check_mark: | :x: |\n| CBC | :heavy_check_mark: | :x: |\n| CFB | :heavy_check_mark: | :heavy_check_mark: |\n| OFB | :heavy_check_mark: | :heavy_check_mark: |\n| CTR | :x: | :x: |\n\nDevelopment status:\n\n- [x] VHDL design\n- [x] Functional simulation\n- [x] Implementation\n- [ ] Test on FPGA (it was reported that the design was successfully ran on an Altera Max 10 Board at 50 MHz)\n\n## Usage\n\nThe core expects key, iv (optional) and plaintext/ciphertext (depending if encrypting or decrypting) through `islv_data`. A new set of key and iv should be signalised by assigning `isl_new_key_iv` for one cycle. Valid inputs should be marked by assigning the `isl_valid` signal. Accordingly, the output `oslv_data` is valid when the signal `osl_valid` is assigned. New input data can be transmitted only when the output is fully done.\n\nExample for AES-256 encryption in CFB mode with an interface bitwidth of 32 bit:\n\n![AES toplevel waveform](https://svg.wavedrom.com/github/marph91/yaaes/add-usage-and-documentation/doc/aes_toplevel_waveform.json)\n\n## Resource usage\n\nThe following results are obtained from a local synthesis for Lattice ECP5, using the open source toolchain (ghdl, yosys and nextpnr). For more details, see the synthesis workflow.\n\n- Device: ULX3S\n- Configuration: as in the example above\n- Results:\n  - Resources:\n    - TRELLIS_SLICE:  3109/41820     7%\n    - DCCA:              1/   56     1%\n  - Target frequency: 100 MHz\n  - Maximum frequency: 121 MHz\n\n## Performance\n\nFrom the testsuite runs, the following metrics can be derived (configuration as above):\n\n- Latency: 37 cycles (after initial key and iv transmission)\n- Throughput: One input of 128 bit each 42 cycles \u0026rarr; 3 bit per clock cycle \u0026rarr; 300 Mbps at 100 MHz\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmarph91%2Fyaaes","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmarph91%2Fyaaes","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmarph91%2Fyaaes/lists"}