{"id":13398861,"url":"https://github.com/masc-ucsc/livehd","last_synced_at":"2025-03-14T03:30:48.758Z","repository":{"uuid":"130754579","full_name":"masc-ucsc/livehd","owner":"masc-ucsc","description":"Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation","archived":false,"fork":false,"pushed_at":"2024-04-13T13:57:10.000Z","size":125394,"stargazers_count":196,"open_issues_count":11,"forks_count":46,"subscribers_count":28,"default_branch":"master","last_synced_at":"2024-04-13T21:02:47.950Z","etag":null,"topics":["asic","fpga","hdl","lgraph","live","simulation","synthesis"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/masc-ucsc.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"docs/CONTRIBUTING.md","funding":null,"license":"LICENSE","code_of_conduct":"docs/CODE_OF_CONDUCT.md","threat_model":null,"audit":null,"citation":"CITATION.cff","codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2018-04-23T20:44:49.000Z","updated_at":"2024-04-16T04:38:28.677Z","dependencies_parsed_at":"2023-10-28T04:21:40.780Z","dependency_job_id":"a95ef66d-4f69-4b50-aad7-0a4f4028eb39","html_url":"https://github.com/masc-ucsc/livehd","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/masc-ucsc%2Flivehd","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/masc-ucsc%2Flivehd/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/masc-ucsc%2Flivehd/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/masc-ucsc%2Flivehd/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/masc-ucsc","download_url":"https://codeload.github.com/masc-ucsc/livehd/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":197206500,"owners_count":13310263,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","fpga","hdl","lgraph","live","simulation","synthesis"],"created_at":"2024-07-30T19:00:32.277Z","updated_at":"2024-07-30T19:03:09.532Z","avatar_url":"https://github.com/masc-ucsc.png","language":"Verilog","funding_links":[],"categories":["Projects (sorted by year)","C++","Circuit Compilers"],"sub_categories":["2018"],"readme":null,"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmasc-ucsc%2Flivehd","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmasc-ucsc%2Flivehd","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmasc-ucsc%2Flivehd/lists"}