{"id":18359542,"url":"https://github.com/matrixsmaster/nanorvi","last_synced_at":"2025-04-10T03:23:28.721Z","repository":{"id":151653403,"uuid":"309139696","full_name":"matrixsmaster/NanoRVI","owner":"matrixsmaster","description":"A very minimalistic implementation of RISC-V 32i ISA, capable of running serious code.","archived":false,"fork":false,"pushed_at":"2021-07-20T07:34:03.000Z","size":2206,"stargazers_count":2,"open_issues_count":0,"forks_count":1,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-02-15T18:39:26.216Z","etag":null,"topics":["emulation","minimalistic","risc-v"],"latest_commit_sha":null,"homepage":"https://gitlab.com/sciloaf/NanoRVI","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/matrixsmaster.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-11-01T16:36:27.000Z","updated_at":"2024-11-03T09:03:30.000Z","dependencies_parsed_at":null,"dependency_job_id":"274d2090-12c5-4ac2-867f-632d97c285ab","html_url":"https://github.com/matrixsmaster/NanoRVI","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/matrixsmaster%2FNanoRVI","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/matrixsmaster%2FNanoRVI/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/matrixsmaster%2FNanoRVI/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/matrixsmaster%2FNanoRVI/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/matrixsmaster","download_url":"https://codeload.github.com/matrixsmaster/NanoRVI/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248149206,"owners_count":21055732,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["emulation","minimalistic","risc-v"],"created_at":"2024-11-05T22:23:15.349Z","updated_at":"2025-04-10T03:23:28.672Z","avatar_url":"https://github.com/matrixsmaster.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"## NanoRVI - a very minimalistic implementation of RISC-V 32i ISA emulator, capable of running serious code\n\nProbably the simpleset implementation in the existence. The emulation core is only about 288 lines of pure C code. And it's completely embeddable into your own projects.\n\nI made this implementation to make myself more comfortable with RV32I ISA, and to have a bit of fun. However, I'm now planning to use this in my other projects as well.\n\n### Testing the ISA\n\nIncluded in `tests/suite` directory, you'll find a version of the [official RISC-V test suite](https://github.com/riscv/riscv-tests) which I modified to run well with my emulator.\nUse `do.sh` script to run through all instruction tests automatically.\n\n### Reusing the code\n\nIf you want to embed this emulator into your own project, all you need to do is:\n\n1. Copy 3 files (riscv.c; riscv.h; riscv_tabs.h) into your project source tree\n2. Implement virtual memory read/write functions:\n\n    1. `read(8/16/32)` - simple __unsigned__ read\n    2. `write(8/16/32)` - simple __unsigned__ write\n\n3. Implement service functions:\n\n    1. `ecall` - syscall (consult RISC-V toolchain's syscall.h)\n    2. `ebreak` - your breakpoint implementation (just an empty function in the simplest case)\n\n4. Initialize `riscv_state` structure and use it when calling `riscv_exec()`\n\nThe emulator core is completely re-entrant, so you can enjoy running thousands of virtual RISC-V CPUs in parallel on your mighty GPU ;)\n\n___Copyright (C) Dmitry 'MatrixS_Master' Solovyev, 2020-2021. All rights reserved.___\n\n___This work is licensed under the MIT License. See included LICENSE file___\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmatrixsmaster%2Fnanorvi","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmatrixsmaster%2Fnanorvi","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmatrixsmaster%2Fnanorvi/lists"}