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`nl-compiler`: Frontend Compiler for [Safety-Net](https://github.com/matth2k/safety-net)\n\n## Getting Started\n\nBelow is a minimal example to get you started:\n\n```verilog\nmodule and_test (\n    a,\n    b,\n    y\n);\n  input a;\n  wire a;\n  input b;\n  wire b;\n  output y;\n  wire y;\n\n  AND _0_ (\n      .A(a),\n      .B(b),\n      .Y(y)\n  );\n\nendmodule\n```\n\nSave the above file to `and.v`.\n\n`cargo run --example roundtrip -- and.v`\n\nAlso, take a look at some of the [tests](https://github.com/matth2k/nl-compiler/blob/main/tests/verilog.rs):\n\n```rust\n#[test]\nfn mux_lut() {\n    let src = \"module lut_test (\n                           a,\n                           b,\n                           c,\n                           y\n                       );\n                         input a;\n                         wire a;\n                         input b;\n                         wire b;\n                         input c;\n                         wire c;\n                         output y;\n                         wire y;\n                       \n                         LUT3 #(\n                             .INIT(8'b11001010)\n                         ) _0_ (\n                             .I0(a),\n                             .I1(b),\n                             .I2(c),\n                             .O(y)\n                         );\n                       \n                       endmodule\n                       \"\n    .to_string();\n\n    assert_verilog_eq!(src, roundtrip(\u0026src).unwrap());\n}\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmatth2k%2Fnl-compiler","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmatth2k%2Fnl-compiler","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmatth2k%2Fnl-compiler/lists"}