{"id":17865072,"url":"https://github.com/mattvenn/fpga-dvid-ice","last_synced_at":"2026-01-30T20:32:12.119Z","repository":{"id":143164643,"uuid":"80522626","full_name":"mattvenn/fpga-dvid-ice","owner":"mattvenn","description":null,"archived":false,"fork":false,"pushed_at":"2017-02-24T18:46:51.000Z","size":256,"stargazers_count":10,"open_issues_count":0,"forks_count":2,"subscribers_count":4,"default_branch":"master","last_synced_at":"2026-01-14T19:33:02.030Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mattvenn.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2017-01-31T13:26:56.000Z","updated_at":"2023-01-02T11:33:50.000Z","dependencies_parsed_at":"2023-05-19T12:00:57.005Z","dependency_job_id":null,"html_url":"https://github.com/mattvenn/fpga-dvid-ice","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/mattvenn/fpga-dvid-ice","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Ffpga-dvid-ice","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Ffpga-dvid-ice/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Ffpga-dvid-ice/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Ffpga-dvid-ice/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mattvenn","download_url":"https://codeload.github.com/mattvenn/fpga-dvid-ice/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Ffpga-dvid-ice/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28918451,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-30T20:25:28.696Z","status":"ssl_error","status_checked_at":"2026-01-30T20:25:13.426Z","response_time":66,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-10-28T09:18:25.539Z","updated_at":"2026-01-30T20:32:12.077Z","avatar_url":"https://github.com/mattvenn.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# DVI-D in Verilog use IceStorm open tools\n\nMinimal DVI-D output based on Mike Field's work (see credits below).\n\nTMDS output is not supported by the lattice chip on the icestick and mystorm\nboards. Unable to get good enough signals with a breadboard so [made a\nPCB](https://github.com/mattvenn/kicad/tree/master/dvi-pmod) which shows\npromise.\n\n[pictures](https://goo.gl/photos/ScRRi142sbwstPGr6)\n\n# Current status\n\n* green screen output 640 x 480 @ 60Hz!\n* test patterns have some problems - unsure what is happening\n* very unstable - small changes to vga timings have big effects\n* 'converting' LVDS to TMDS with [resistors and capacitors](https://github.com/mattvenn/kicad/tree/master/dvi-pmod)\n\n## GTKwave traces\n\nI think these show that the verilog is correct, at least it is what I expect.\n\nShows correct TMDS symbols for blanking\n\n![blanking](docs/blank.png)\n\nShows correct TMDS for hsync\n\n![hsync](docs/hsync.png)\n\nShows correct TMDS for RGB = 000, 001, 111.\n\n![rgb](docs/rgb.png)\n\n## Scope pics\n\nFollowing pics are with the x5 clock for DVI output set to 50MHz (target is\n200MHz). Top 4 traces are Clock, R, G, B. Bottom 5 traces are 12MHz clock, DVI\nclock (50MHz), VGA clock (10MHz), blank, vsync, hsync.\n\nHsync and Vsync zoomed out\n\n![hsync and vsync zoomed out](docs/TEK00001.PNG)\n\nHsync zoomed in\n\n![hsync zoomed in](docs/TEK00002.PNG)\n\nI can just about read the lines, it would be good to see the logic levels\nrecovered by the monitor when adding the negative sides of the signals.\n\n## Electrical connections\n\n* Breadboarded version [current messy\nstatus](https://goo.gl/photos/bQrL8b5GGyBhnb3S8) didn't work.\n* New PMOD DVID PCB shows promise.\n\n# Resources / Credits\n\nlots of thanks to Mike Field of [hamsterworks](http://hamsterworks.co.nz) for\ngreat resources on dvi and vga. Here are some resources I've used in developing\nthis project.\n\n* http://hamsterworks.co.nz/mediawiki/index.php/VGA_timings\n* http://hamsterworks.co.nz/mediawiki/index.php/FPGA_VGA\n* https://github.com/jeelabs/fpga/blob/master/quartus/vga1024/top.vga\n* ice storm: http://www.clifford.at/icestorm/\n* [TMDS/LVDS question](http://electronics.stackexchange.com/questions/130942/transmitting-hdmi-dvi-over-an-fpga-with-no-support-for-tmds) Link to silabs pdf shows a way to interface between LVDS and TMDS with R and 2xC\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmattvenn%2Ffpga-dvid-ice","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmattvenn%2Ffpga-dvid-ice","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmattvenn%2Ffpga-dvid-ice/lists"}