{"id":13649360,"url":"https://github.com/mattvenn/fpga-sdft","last_synced_at":"2026-02-19T16:02:10.189Z","repository":{"id":143164644,"uuid":"136205751","full_name":"mattvenn/fpga-sdft","owner":"mattvenn","description":"sliding DFT for FPGA, targetting Lattice ICE40 1k","archived":false,"fork":false,"pushed_at":"2020-04-24T11:34:55.000Z","size":187,"stargazers_count":76,"open_issues_count":1,"forks_count":16,"subscribers_count":7,"default_branch":"master","last_synced_at":"2026-01-14T19:33:02.030Z","etag":null,"topics":["fft","fourier","fpga","icestorm","sdft","verilog","yosys"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mattvenn.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2018-06-05T16:31:58.000Z","updated_at":"2025-10-08T12:39:58.000Z","dependencies_parsed_at":"2023-04-18T17:05:46.439Z","dependency_job_id":null,"html_url":"https://github.com/mattvenn/fpga-sdft","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/mattvenn/fpga-sdft","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Ffpga-sdft","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Ffpga-sdft/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Ffpga-sdft/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Ffpga-sdft/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mattvenn","download_url":"https://codeload.github.com/mattvenn/fpga-sdft/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Ffpga-sdft/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29621897,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-19T13:04:20.082Z","status":"ssl_error","status_checked_at":"2026-02-19T13:03:33.775Z","response_time":117,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fft","fourier","fpga","icestorm","sdft","verilog","yosys"],"created_at":"2024-08-02T01:04:57.947Z","updated_at":"2026-02-19T16:02:10.154Z","avatar_url":"https://github.com/mattvenn.png","language":"Verilog","funding_links":[],"categories":["Verilog"],"sub_categories":[],"readme":"# FFT on an FPGA\n\nhaving a go at some DSP on an FPGA. I'm basing the design on this paper:\n\nhttp://www.comm.toronto.edu/~dimitris/ece431/slidingdft.pdf\n\nThis is a sliding discrete Fourier transform. It requires two real adds and one complex multiply per frequency bin. The transform is run for every new sample taken.\n\n![overview](docs/sdft.png)\n\n![sdft vs fft](docs/fft_vs_sdft.png)\n\n# Makefile\n\n* make list - compute the twiddle factor tables\n* make show-sdft - use yosys show to see how the design is inferred\n* make debug-sdft - use iverilog, vvp and gtkwave to show the results of the testbench\n* make read-sdft-vcd - after vcd generated, use Python script to read the vcd and plot the last set of results computed\n* make model-sdft - model sdft in python and compare against numpy's fft\n* make - build everything\n* make prog - program the icestick\n\n# Done\n\n* Read the resources\n* Implement HDL twiddle factor ROM\n* Implement an [SDFT in Python](python/sdft.py) using the same pattern\n* Why doesn't makefile build from scratch? - missing a file\n* Why do freq bin regs overflow almost immediately in the testbench? scaling\n* How to do scaling - the twiddle factors are scaled to fill the hole register so things overflow quickly, divide by 127\n* Why doesn't pnr work? - it does, but the module wasn't being used so yosys was removing it\n* make the python tools parse test/localparams.vh  - very basic but works OK\n* adc connected, pinout is correct. sampleing has to be done on clock negedge\n\n# Todo\n\n* how to deal with timing analysis being lower than the clock I'm using\n\n# FPGA resources used\n\nUsing an 8k device:\n\n    IOs          18 / 206\n    GBs          0 / 8\n      GB_IOs     0 / 8\n    LCs          3619 / 7680\n      DFF        120\n      CARRY      512\n      CARRY, DFF 39\n      DFF PASS   86\n      CARRY PASS 165\n    BRAMs        13 / 32\n    WARMBOOTs    0 / 1\n    PLLs         1 / 2\n\n# Resources\n\n* great video that explains what the Fourier transform is: https://www.youtube.com/watch?v=spUNpyF58BY\n* paper on implementing an FFT on an FPGA http://web.mit.edu/6.111/www/f2017/handouts/FFTtutorial121102.pdf\n* using Python to implement FFT: https://jakevdp.github.io/blog/2013/08/28/understanding-the-fft/\n* sliding FFT https://www.dsprelated.com/showarticle/776.php\n* stackoverflow answer about sdft: https://stackoverflow.com/questions/6663222/doing-fft-in-realtime\n* paper on SDFT: http://www.comm.toronto.edu/~dimitris/ece431/slidingdft.pdf\n* http://www.analog.com/media/en/technical-documentation/data-sheets/AD9283.pdf\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmattvenn%2Ffpga-sdft","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmattvenn%2Ffpga-sdft","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmattvenn%2Ffpga-sdft/lists"}