{"id":17865031,"url":"https://github.com/mattvenn/mph-tristate-test","last_synced_at":"2026-01-12T02:13:42.983Z","repository":{"id":143164732,"uuid":"328735520","full_name":"mattvenn/mph-tristate-test","owner":"mattvenn","description":null,"archived":false,"fork":false,"pushed_at":"2021-01-26T17:03:39.000Z","size":2539,"stargazers_count":4,"open_issues_count":0,"forks_count":1,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-04-01T18:09:54.716Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mattvenn.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-01-11T17:08:43.000Z","updated_at":"2022-03-17T00:19:42.000Z","dependencies_parsed_at":null,"dependency_job_id":"3a351fda-0f1e-4a0f-914d-59cd358163bb","html_url":"https://github.com/mattvenn/mph-tristate-test","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Fmph-tristate-test","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Fmph-tristate-test/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Fmph-tristate-test/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Fmph-tristate-test/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mattvenn","download_url":"https://codeload.github.com/mattvenn/mph-tristate-test/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246895697,"owners_count":20851317,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-10-28T09:18:15.846Z","updated_at":"2026-01-12T02:13:42.908Z","avatar_url":"https://github.com/mattvenn.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Multi Project Wrapper v2\n\n## Aim\n\n* Allow many (\u003c20) designers to combine their small design into a single application to the Google/Efabless/Skywater ASIC  shuttle.\n* Compartmentalise the designs and allow them to be activated in turn.\n* Each design should have access to all the I/O and [Caravel](https://github.com/efabless/caravel) wishbone bus.\n\n## Version 1 issues\n\n* The last version (submitted on first shuttle) used a MUX, which had a star topology. \n* Due to restrictions in the OpenLANE ASIC flow, all the designs had to be instantiated at the top level, then routed out to the MUX, then back to the IO.\n* Each design had a different interface that required a unique instantiation. This was pretty ugly and prone to errors. \n* The MUX block had to be long and thin to fit all the pins (~3k) around the edges.\n\n## Improvements\n\n* Unify interface.\n* Use bus topology with tristated outputs on each design, reducing routing congestion.\n* Formal [proof of tristate](properties.v) that can be run as part of CI.\n\n## Proposal\n\n![schematic](docs/mph.jpg)\n\n* Each project gets instantiated inside the [wrapper.v](wrapper.v)\n* Wrapper provides unified interface with ~320 pins: all IO, all wishbone, reduced logic analyser (logic analyser is firmware controlled by [caravel harness picorv32](https://github.com/efabless/caravel)).\n* Individual wrappers are activated by [logic analyser pins](https://github.com/mattvenn/tristate-test/blob/ee7369ed6f704a73b9106e8bdbadb4eda9e9325b/user_project_wrapper.v#L133) not connected to the wrapper.\n* All the wrappers get instantiated by [user_project_wrapper.v](user_project_wrapper.v) (this is part of the Efabless harness and can't be changed.\n\n## Individual wrapper results\n\n* wrapper.v tested with simple 7 segment demo. \n* used [config](configs/wrapper/config.tcl) to make die size 200um x 200um\n\n### wrapper : DESIGN=wrapper RUN_DATE=14-01_15-49\n\n        tritonRoute_violations :                    0\n              Short_violations :                    0\n             MetSpc_violations :                    0\n            OffGrid_violations :                    0\n            MinHole_violations :                    0\n              Other_violations :                    0\n              Magic_violations :                    0\n            antenna_violations :                    1\n              lvs_total_errors :                    0\n              cvc_total_errors :                    0\n\nwidth x height 200 um\n\n## Simulation\n\nSimulation shows startup, no design active, 1st design active, 2nd design active.\n\n    make sim # requires cocotb\n    gtkwave user_project_wrapper.vcd  user_project_wrapper.gtkw\n\n![simulation](docs/simulation.png)\n\n## OpenLANE Results - user_project_wrapper with 16 projects \n\nInitial results look good. The OpenLANE flow was able to route 16 designs with only a few errors that are currently being investigated.\n\n![gds](docs/gds.png)\n\nPicture shows output pin connecting to an ebuf tristate cell.\n\n![gds-ebuf](docs/ebuf-gds.png)\n\nYosys [cell usage report](docs/yosys_2.stat.rpt) includes 141 [sky130_fd_sc_hd__ebufn_2 tristate buffers](https://antmicro-skywater-pdk-docs.readthedocs.io/en/86-cell_cross_index/contents/libraries/sky130_fd_sc_hd/cells/ebufn/README.html) in use for individual wrapper macro.\n\nSome [config](configs/user_project_wrapper) were created with Python [placer.py](configs/user_project_wrapper/placer.py) script.\n\n## To resolve\n\n* [Yosys report](docs/yosys_.chk.rpt) reports multiple conflicting drivers for all the tristated outputs.\n* run a gate level simulation\n* 25 DRC issues\n* netlist match LVS issues\n\n# Design Review\n\n## Ahmed\n\n* tristate hand placed (rather than inferred), to keep mindful, make it explicit\n* better include tristate inside macro not outside to keep it the most similar as before\n* use rc6 for testing\n* cts outside and design uses external slow clock divider module\n* ref for handplaced tristate https://github.com/shalan/DFFRAM/blob/main/Handcrafted/Models/DFFRAMBB.v#L205\n\n## tnt\n\n* ditch la, or most of it\n* use opendb to do the bus routing and connections?\n* esd diodes on inputs + buffers of tri block for protection and isolation\n* looks good\n\n# Log\n\n## Wed 20 Jan 16:07:20 CET 2021\n\nTrying to solve the 30-\u003e60 shorts I'm getting with tritonroute\n\n* tried telling tritonroute to use less resources on the first 2 layers:\n    set ::env(GLB_RT_L2_ADJUSTMENT) 0.2\n    set ::env(GLB_RT_L3_ADJUSTMENT) 0.2\n* tried setting pin order, made little difference\n* tried increasing die size to 300um x 300um to increase distance between pins\n\n## Thu 21 Jan 13:22:42 CET 2021\n\n* made a minimal example in minimal branch, all contained in one module\n* ran openlane and got no warnings\n* Gate level simulation works, must provide power\n* tried gatelevel sim of user_project_wrapper, works\n* think that the warnings are because wrappers are already hardened and bboxed, so yosys doesn't know they are tristated outs\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmattvenn%2Fmph-tristate-test","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmattvenn%2Fmph-tristate-test","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmattvenn%2Fmph-tristate-test/lists"}