{"id":17864941,"url":"https://github.com/mattvenn/vga-clock","last_synced_at":"2026-02-25T05:41:13.813Z","repository":{"id":37347063,"uuid":"278571718","full_name":"mattvenn/vga-clock","owner":"mattvenn","description":"Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.","archived":false,"fork":false,"pushed_at":"2021-11-05T11:32:17.000Z","size":1548,"stargazers_count":62,"open_issues_count":1,"forks_count":12,"subscribers_count":3,"default_branch":"master","last_synced_at":"2026-01-14T19:33:05.835Z","etag":null,"topics":["fpga","rtl","simulation","verilog"],"latest_commit_sha":null,"homepage":"https://www.zerotoasiccourse.com/post/vga_clock/","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mattvenn.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE-2.0.txt","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-07-10T07:44:51.000Z","updated_at":"2025-06-26T22:17:32.000Z","dependencies_parsed_at":"2022-09-12T23:42:31.628Z","dependency_job_id":null,"html_url":"https://github.com/mattvenn/vga-clock","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/mattvenn/vga-clock","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Fvga-clock","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Fvga-clock/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Fvga-clock/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Fvga-clock/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mattvenn","download_url":"https://codeload.github.com/mattvenn/vga-clock/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mattvenn%2Fvga-clock/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29811592,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-25T05:36:42.804Z","status":"ssl_error","status_checked_at":"2026-02-25T05:36:31.934Z","response_time":61,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","rtl","simulation","verilog"],"created_at":"2024-10-28T09:17:39.776Z","updated_at":"2026-02-25T05:41:13.771Z","avatar_url":"https://github.com/mattvenn.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# VGA Clock\n\nsimple project to show the time on a 640x480 VGA display.\n\n![vga clock](docs/vga_clock.jpg)\n\n## Simulation instructions\n\nEnsure that you have libsdl2-dev and verilator installed.\n\n    sudo apt-get install libsdl2-dev libsdl2-image-dev verilator\n\nTo run the simulation use the following commands:\n\n    cd rtl\n    make verilator \u0026\u0026 ./obj_dir/Vvga_clock\n\n![fb_verilator](docs/fb_verilator.png)\n\nUse the h, m and s keys to increment the hour, minute and second counters respectively.\n\n## FPGA Build instructions\n\nIt's setup to run on [1 Bit Squared icebreaker](https://1bitsquared.com/products/icebreaker) with my [VGA pmod](https://github.com/mattvenn/6bit-pmod-vga) plugged into pmod1a.\n\ntype\n\n    make prog\n\nto build \u0026 upload to the icebreaker\n\n## FPGA utilisation\n\nusing [logLUTs](https://github.com/mattvenn/logLUTs) to record resource usage and max frequency over commits:\n\n![luts](docs/luts.png)\n\n## ASIC utilisation\n\nhttps://www.zerotoasiccourse.com/post/vga_clock/\n\nusing the [Skywater/Google 130nm](https://github.com/google/skywater-pdk) process and [OpenLane](https://github.com/efabless/openlane)\n\n* copy contents of rtl directory to designs/vga_clock/src/\n* remove digit_tb.v and top_tb.v from designs/vga_clock/src/ (I am working on separating test and rtl)\n* copy asic/config.tcl to designs/vga_clock/\n* inside the docker environment:\n    * run ./flow.tcl -init_design_config -design vgaclock\n    * run ./flow.tcl -design vga_clock\n\nThis results in a routed design that uses 180x180 microns.\n\nSee [asic/Makefile](asic/Makefile) for some rules that start the docker and show the finished GDS in magic or klayout.\n\n![full die](docs/asic-full.png)\n\n![zoom top left](docs/asic-zoom.png)\n\n## License\n\nThis software and hardware is licensed under the [Apache License version 2](LICENSE-2.0.txt)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmattvenn%2Fvga-clock","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmattvenn%2Fvga-clock","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmattvenn%2Fvga-clock/lists"}