{"id":25663784,"url":"https://github.com/maxxsoft/fuxi","last_synced_at":"2025-06-17T20:40:21.711Z","repository":{"id":40457625,"uuid":"235326677","full_name":"MaxXSoft/Fuxi","owner":"MaxXSoft","description":"Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.","archived":false,"fork":false,"pushed_at":"2021-06-28T08:13:27.000Z","size":1726,"stargazers_count":170,"open_issues_count":0,"forks_count":23,"subscribers_count":4,"default_branch":"master","last_synced_at":"2025-03-29T14:41:27.894Z","etag":null,"topics":["chisel","cpu","fpga","riscv","scala"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/MaxXSoft.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-01-21T11:29:30.000Z","updated_at":"2025-03-13T03:18:41.000Z","dependencies_parsed_at":"2022-07-09T04:46:01.060Z","dependency_job_id":null,"html_url":"https://github.com/MaxXSoft/Fuxi","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MaxXSoft%2FFuxi","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MaxXSoft%2FFuxi/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MaxXSoft%2FFuxi/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MaxXSoft%2FFuxi/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/MaxXSoft","download_url":"https://codeload.github.com/MaxXSoft/Fuxi/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250233638,"owners_count":21396837,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chisel","cpu","fpga","riscv","scala"],"created_at":"2025-02-24T05:19:02.505Z","updated_at":"2025-04-22T11:36:29.903Z","avatar_url":"https://github.com/MaxXSoft.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Fuxi\n\n[![Test](https://github.com/MaxXSoft/Fuxi/workflows/Test/badge.svg)](https://github.com/MaxXSoft/Fuxi)\n\nFuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.\n\n![datapath](img/datapath.svg)\n\n## Implemented ISAs\n\n* RV32I 2.1\n* Zifencei extension 2.0\n* Zicsr extension 2.0\n* M extension 2.0\n* A extension 2.0\n* Machine-level ISA 1.11\n* Supervisor-level ISA 1.11\n\n## Unimplemented Details\n\nFuxi processor is designed for running [GeeOS](https://github.com/MaxXSoft/GeeOS), or other simple operating systems or bare-metal software. Considering the complexity, the following functions has not yet been implemented:\n\n* Memory privilege in `mstatus` register: `MPRV` bit and `MXR` bit are hardwired to 0.\n* Virtualization support in `mstatus` register: `TVM` bit, `TW` bit and `TSR` bit are hardwired to 0.\n* Physical Memory Protection: all PMP registers are hardwired to 0.\n\n## Performance\n\nWith default configuration:\n\n* **Dhrystone 2.1**: 0.60 DMIPS/MHz.\n* **CoreMark**: 2.15 CoreMark/MHz.\n\n## Getting Started\n\nBy issuing the following command lines, you can get generated verilog file in directory `verilog/build`:\n\n```\n$ git clone https://github.com/MaxXSoft/Fuxi\n$ cd Fuxi\n$ make\n```\n\n## Running Tests\n\n### Running Unit Tests\n\nAll unit tests are available in directory `src/test/scala`. For example, unit test for decode stage is available in `core/DecoderTest.scala`, you can run this test by executing the following command lines:\n\n```\n$ sbt\n\u003e test:runMain core.DecoderTest\n```\n\n### Running `CoreTest`\n\n`CoreTest` is a special unit test provided in this repository, it can run simple RISC-V programs using the Fuxi core. We also provided some programs in directory `src/test/resources`. For example, you can run one of it:\n\n```\n$ sbt\n\u003e test:runMain core.CoreTest -if src/test/resources/fib.txt\n```\n\nTrace information during running program `fib.txt` will be printed to the console.\n\n`CoreTest` supports the following command line arguments:\n\n| Option          | Abbreviation  | Argument              | Description\n| -               | -             | -                     | -\n| `--init-file`   | `-if`         | path to program file  | Specify the initialization file of ROM.\n| `--trace-file`  | `-tf`         | path to trace file    | Specify the trace file, default to empty.\n| `--gen-trace`   | `-gt`         | 0 or other values     | Set to 0 for trace comparison, otherwise use Fuxi core to generate trace file. Default to 0.\n\nSo you can test the core using a trace file generated by other processor or emulator:\n\n```\n\u003e test:runMain core.CoreTest -if src/test/resources/fib.txt -tf src/test/resources/fib_trace.txt\n```\n\nFor other details, please read [the source file](src/test/scala/core/CoreTest.scala) of `CoreTest.scala`.\n\nAll provided programs:\n\n| Name        | Description\n| -           | -\n| fib.txt     | Generate the first 10 terms of the Fibonacci sequence.\n| mdu.txt     | Perform some multiplications and divisions.\n| mecall.txt  | Test machine mode environment call.\n| secall.txt  | Test supervisor mode environment call.\n\n### Running Other Test Benches\n\n\u003e This part is under construction.\n\nAs we see in [the top level module](src/main/scala/Fuxi.scala), the complete Fuxi processor consists of `Core` and `CoreBus`, the latter provides MMU, cache system and AXI4 interface for the `Core` part.\n\nAll of the unit test cases currently contained in this repository can only test modules in the `Core` part, we are still preparing the test bench the entire processor system. For now, you can build a tiny SoC by yourself based on some AXI4 IP cores to run other test benches you want.\n\n## Copyright and License\n\nCopyright (C) 2010-2020 MaxXing. License GPLv3.\n\nSpecial thanks to [@Yukiteru Lee](https://github.com/wfly1998/).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmaxxsoft%2Ffuxi","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmaxxsoft%2Ffuxi","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmaxxsoft%2Ffuxi/lists"}