{"id":27405008,"url":"https://github.com/maze1377/pipeline-mips-verilog","last_synced_at":"2026-02-02T15:03:18.568Z","repository":{"id":64266599,"uuid":"195538902","full_name":"maze1377/pipeline-mips-verilog","owner":"maze1377","description":"A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall","archived":false,"fork":false,"pushed_at":"2025-01-28T19:47:45.000Z","size":235,"stargazers_count":49,"open_issues_count":0,"forks_count":8,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-06-10T21:10:33.864Z","etag":null,"topics":["control-hazards","data-hazards","mips","mips-architecture","mips-instruction","mips32","pipeline-mips-verilog","pipline","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/maze1377.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2019-07-06T12:49:22.000Z","updated_at":"2025-05-28T03:33:55.000Z","dependencies_parsed_at":"2025-04-14T05:49:06.250Z","dependency_job_id":"0c93642e-e54a-48cc-b5c1-7b8827989f50","html_url":"https://github.com/maze1377/pipeline-mips-verilog","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/maze1377/pipeline-mips-verilog","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/maze1377%2Fpipeline-mips-verilog","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/maze1377%2Fpipeline-mips-verilog/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/maze1377%2Fpipeline-mips-verilog/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/maze1377%2Fpipeline-mips-verilog/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/maze1377","download_url":"https://codeload.github.com/maze1377/pipeline-mips-verilog/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/maze1377%2Fpipeline-mips-verilog/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29013715,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-02T14:58:54.169Z","status":"ssl_error","status_checked_at":"2026-02-02T14:58:51.285Z","response_time":58,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["control-hazards","data-hazards","mips","mips-architecture","mips-instruction","mips32","pipeline-mips-verilog","pipline","verilog"],"created_at":"2025-04-14T05:49:01.086Z","updated_at":"2026-02-02T15:03:18.561Z","avatar_url":"https://github.com/maze1377.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"\n# MIPS pipline\nA classic 5-stage pipeline MIPS 32-bit processor.\n\nfive stages of a microprocessor: instruction fetch (IF),\ninstruction decode (ID), execution(EX),\nmemory access and write (MEM) e write back (WB).\n\n#name of wire and guideline\t\t\n![wirename](https://github.com/maze1377/pipeline-mips-verilog/blob/master/screenshots/guidline.jpg)\n\n#states\n![state](https://github.com/maze1377/pipeline-mips-verilog/blob/master/screenshots/state.png)\n\nsupport most of MIPS instruction and solve every hazard with stall.(Data Hazards and Control Hazards) Verilog code.\n\nDeveloped during the winter 2019 Computer Architecture Laboratory course at the University of Ferdowsi Mashhad.\n# Modular design\ncode start from mypip\n\nother modular named same to original model\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmaze1377%2Fpipeline-mips-verilog","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmaze1377%2Fpipeline-mips-verilog","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmaze1377%2Fpipeline-mips-verilog/lists"}