{"id":18054126,"url":"https://github.com/mbuesch/crcgen","last_synced_at":"2025-04-10T22:53:37.450Z","repository":{"id":39669653,"uuid":"199708204","full_name":"mbuesch/crcgen","owner":"mbuesch","description":"Generator for CRC HDL code (VHDL, Verilog, MyHDL)","archived":false,"fork":false,"pushed_at":"2023-10-13T20:58:51.000Z","size":116,"stargazers_count":35,"open_issues_count":0,"forks_count":9,"subscribers_count":3,"default_branch":"master","last_synced_at":"2025-04-10T15:17:05.021Z","etag":null,"topics":["crc","crc-algorithms","crc-calculation","crc32","myhdl","verilog","vhdl"],"latest_commit_sha":null,"homepage":"https://bues.ch/h/crcgen","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mbuesch.png","metadata":{"files":{"readme":"README.rst","changelog":null,"contributing":null,"funding":null,"license":"COPYING","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null}},"created_at":"2019-07-30T18:42:16.000Z","updated_at":"2025-04-04T18:56:46.000Z","dependencies_parsed_at":"2023-10-14T21:26:57.897Z","dependency_job_id":null,"html_url":"https://github.com/mbuesch/crcgen","commit_stats":null,"previous_names":[],"tags_count":9,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mbuesch%2Fcrcgen","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mbuesch%2Fcrcgen/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mbuesch%2Fcrcgen/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mbuesch%2Fcrcgen/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mbuesch","download_url":"https://codeload.github.com/mbuesch/crcgen/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248243862,"owners_count":21071113,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["crc","crc-algorithms","crc-calculation","crc32","myhdl","verilog","vhdl"],"created_at":"2024-10-31T00:09:23.011Z","updated_at":"2025-04-10T22:53:37.423Z","avatar_url":"https://github.com/mbuesch.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"CRC algorithm HDL code generator (VHDL, Verilog, MyHDL)\n=======================================================\n\n`Homepage \u003chttps://bues.ch/h/crcgen\u003e`_\n\n`Git repository \u003chttps://bues.ch/cgit/crcgen.git\u003e`_\n\n`Github repository \u003chttps://github.com/mbuesch/crcgen\u003e`_\n\nThis tool generates VHDL, Verilog or MyHDL code for use in FPGAs to calculate CRC (Cyclic Redundancy Check) checksums.\n\nThe generated HDL code is synthesizable and combinatorial. That means the calculation runs in one clock cycle on an FPGA.\n\nAny combination of CRC algorithm parameters and polynomial coefficients can be selected.\n\n\nExample usage\n=============\n\nDisplay all options:\n\n.. code:: sh\n\n\tcrcgen -h\n\n\nGenerate Verilog code for CRC-32:\n\n.. code:: sh\n\n\tcrcgen -a CRC-32 -v\n\n\nGenerate VHDL code for CRC-32:\n\n.. code:: sh\n\n\tcrcgen -a CRC-32 -V\n\n\nGenerate Verilog code for a custom non-standard CRC or any standard algorithm that's not included in crcgen's -a list:\n\n.. code:: sh\n\n\tcrcgen -P \"x^8 + x^7 + x^5 + x^4 + x^2 + x + 1\" -B16 -R -v\n\n\nOnline crcgen\n=============\n\nAn easy to use online version of crcgen that can be used without installing or downloading anything to your machine is available here:\n\n`Online crcgen \u003chttps://bues.ch/h/crcgen\u003e`_\n\n\nLicense of the generated HDL code\n=================================\n\nThe generated code is Public Domain.\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\nSPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER\nRESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,\nNEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE\nUSE OR PERFORMANCE OF THIS SOFTWARE.\n\n\nLicense of the generator\n========================\n\nCopyright (c) 2019-2023 Michael Büsch \u003cm@bues.ch\u003e\n\nThis program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.\n\nThis program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmbuesch%2Fcrcgen","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmbuesch%2Fcrcgen","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmbuesch%2Fcrcgen/lists"}