{"id":18054113,"url":"https://github.com/mbuesch/toprammer","last_synced_at":"2025-07-16T18:33:18.149Z","repository":{"id":9789571,"uuid":"11765023","full_name":"mbuesch/toprammer","owner":"mbuesch","description":"TOP2049 Open Source programming suite","archived":false,"fork":false,"pushed_at":"2024-06-28T21:59:07.000Z","size":2631,"stargazers_count":15,"open_issues_count":1,"forks_count":5,"subscribers_count":4,"default_branch":"master","last_synced_at":"2025-07-15T02:46:54.010Z","etag":null,"topics":["burner","eeprom","microcontroller","programmer"],"latest_commit_sha":null,"homepage":"http://bues.ch/cms/hacking/toprammer.html","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mbuesch.png","metadata":{"files":{"readme":"README-DEVELOPERS.lyx","changelog":null,"contributing":null,"funding":null,"license":"COPYING","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2013-07-30T12:55:50.000Z","updated_at":"2025-04-09T10:09:34.000Z","dependencies_parsed_at":"2025-04-10T22:53:44.796Z","dependency_job_id":"bfbd18a5-1b1a-4731-b6e3-44430f77e411","html_url":"https://github.com/mbuesch/toprammer","commit_stats":null,"previous_names":[],"tags_count":19,"template":false,"template_full_name":null,"purl":"pkg:github/mbuesch/toprammer","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mbuesch%2Ftoprammer","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mbuesch%2Ftoprammer/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mbuesch%2Ftoprammer/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mbuesch%2Ftoprammer/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mbuesch","download_url":"https://codeload.github.com/mbuesch/toprammer/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mbuesch%2Ftoprammer/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":265530726,"owners_count":23783138,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["burner","eeprom","microcontroller","programmer"],"created_at":"2024-10-31T00:09:20.222Z","updated_at":"2025-07-16T18:33:18.130Z","avatar_url":"https://github.com/mbuesch.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"#LyX 2.0 created this file. For more info see http://www.lyx.org/\n\\lyxformat 413\n\\begin_document\n\\begin_header\n\\textclass article\n\\use_default_options false\n\\maintain_unincluded_children false\n\\language english\n\\language_package default\n\\inputencoding auto\n\\fontencoding global\n\\font_roman default\n\\font_sans default\n\\font_typewriter default\n\\font_default_family default\n\\use_non_tex_fonts false\n\\font_sc false\n\\font_osf false\n\\font_sf_scale 100\n\\font_tt_scale 100\n\n\\graphics default\n\\default_output_format default\n\\output_sync 0\n\\bibtex_command default\n\\index_command default\n\\paperfontsize default\n\\use_hyperref false\n\\papersize default\n\\use_geometry false\n\\use_amsmath 1\n\\use_esint 1\n\\use_mhchem 1\n\\use_mathdots 1\n\\cite_engine basic\n\\use_bibtopic false\n\\use_indices false\n\\paperorientation portrait\n\\suppress_date false\n\\use_refstyle 0\n\\index Index\n\\shortcut idx\n\\color #008000\n\\end_index\n\\secnumdepth 3\n\\tocdepth 3\n\\paragraph_separation indent\n\\paragraph_indentation default\n\\quotes_language english\n\\papercolumns 1\n\\papersides 1\n\\paperpagestyle default\n\\tracking_changes false\n\\output_changes false\n\\html_math_output 0\n\\html_css_as_file 0\n\\html_be_strict false\n\\end_header\n\n\\begin_body\n\n\\begin_layout Title\nToprammer - Developers guide\n\\end_layout\n\n\\begin_layout Section\nDefinitions\n\\end_layout\n\n\\begin_layout Description\nDUT Device Under Test.\n The device put into the ZIF socket of the programmer\n\\end_layout\n\n\\begin_layout Description\nVPP Programming voltage for the DUT (usually 12V)\n\\end_layout\n\n\\begin_layout Description\nVCC Supply voltage for the DUT\n\\end_layout\n\n\\begin_layout Description\nGND Ground for the DUT\n\\end_layout\n\n\\begin_layout Description\nZIF Zero Insert Force socket of the programmer.\n\\end_layout\n\n\\begin_layout Section\nTOP2049 device hardware\n\\end_layout\n\n\\begin_layout Standard\nThe TOP2049 consists of four basic hardware parts\n\\end_layout\n\n\\begin_layout Itemize\nUSB interface (PDIUSBD12 chip)\n\\end_layout\n\n\\begin_layout Itemize\nMicrocontroller (Megawin MPC89E52A)\n\\end_layout\n\n\\begin_layout Itemize\nFPGA (Xilinx Spartan2 XC2S15)\n\\end_layout\n\n\\begin_layout Itemize\nVCC/GND/VPP supply circuitry\n\\end_layout\n\n\\begin_layout Standard\nThe microcontroller's job is to initialize and communicate to the FPGA and\n set up the VCC/GND/VPP supply circuitry.\n The microcontroller can receive commands via USB interface to do these\n things.\n\\end_layout\n\n\\begin_layout Section\nCommunicating with the programmer via USB\n\\end_layout\n\n\\begin_layout Standard\nIn the \n\\begin_inset Quotes eld\n\\end_inset\n\nmain\n\\begin_inset Quotes erd\n\\end_inset\n\n module there is the \n\\begin_inset Quotes eld\n\\end_inset\n\nclass TOP\n\\begin_inset Quotes erd\n\\end_inset\n\n which is used for communication with the programmer device.\n The class has various methods for hardware access:\n\\end_layout\n\n\\begin_layout Subsection\ncmdRequestVersion()\n\\end_layout\n\n\\begin_layout Standard\nReads the programmer identification and versioning string and returns it.\n\\end_layout\n\n\\begin_layout Subsection\ngetOscillatorHz()\n\\end_layout\n\n\\begin_layout Standard\nReturns the frequency (in Hz) of the oscillator connected to the FPGA clk\n pin.\n\\end_layout\n\n\\begin_layout Subsection\ngetBufferRegSize()\n\\end_layout\n\n\\begin_layout Standard\nReturns the size of the \n\\begin_inset Quotes eld\n\\end_inset\n\nbuffer register\n\\begin_inset Quotes erd\n\\end_inset\n\n.\n\\end_layout\n\n\\begin_layout Subsection\ncmdReadBufferReg(nrBytes=all)\n\\end_layout\n\n\\begin_layout Standard\nReads the \n\\begin_inset Quotes eld\n\\end_inset\n\nbuffer register\n\\begin_inset Quotes erd\n\\end_inset\n\n from the microcontroller.\n That register is used for buffering of data fetched from the FPGA.\n If nrBytes is not specified, it reads the whole register.\n\\end_layout\n\n\\begin_layout Subsection\ncmdReadBufferReg8()\n\\end_layout\n\n\\begin_layout Standard\nSame as cmdReadBufferReg(), but just returns a 8bit int which was formed\n by the first 1 byte of the register.\n\\end_layout\n\n\\begin_layout Subsection\ncmdReadBufferReg16()\n\\end_layout\n\n\\begin_layout Standard\nSame as cmdReadBufferReg(), but just returns a 16bit int which was formed\n by the first 2 bytes of the register (little endian).\n\\end_layout\n\n\\begin_layout Subsection\ncmdReadBufferReg32()\n\\end_layout\n\n\\begin_layout Standard\nSame as cmdReadBufferReg(), but just returns a 32bit int which was formed\n by the first 4 bytes of the register (little endian).\n\\end_layout\n\n\\begin_layout Subsection\ncmdReadBufferReg48()\n\\end_layout\n\n\\begin_layout Standard\nSame as cmdReadBufferReg(), but just returns a 48bit int which was formed\n by the first 6 bytes of the register (little endian).\n\\end_layout\n\n\\begin_layout Subsection\ncmdSetVPPVoltage(voltage)\n\\end_layout\n\n\\begin_layout Standard\nSet VPP (programming voltage) to the specified voltage.\n Voltage is a floating point number.\n\\end_layout\n\n\\begin_layout Subsection\ncmdSetVCCVoltage(voltage)\n\\end_layout\n\n\\begin_layout Standard\nSet VCC (DUT supply voltage) to the specified voltage.\n Voltage is a floating point number.\n\\end_layout\n\n\\begin_layout Subsection\ncmdLoadGNDLayout(layoutID)\n\\end_layout\n\n\\begin_layout Standard\nLoad a ZIF-socket GND-layout.\n You usually don't want to call this directly.\n Use an autogenerated layout instead.\n\\end_layout\n\n\\begin_layout Subsection\ncmdLoadVPPLayout(layoutID)\n\\end_layout\n\n\\begin_layout Standard\nLoad a ZIF-socket VPP-layout.\n You usually don't want to call this directly.\n Use an autogenerated layout instead.\n\\end_layout\n\n\\begin_layout Subsection\ncmdLoadVCCLayout(layoutID)\n\\end_layout\n\n\\begin_layout Standard\nLoad a ZIF-socket VCC-layout.\n You usually don't want to call this directly.\n Use an autogenerated layout instead.\n\\end_layout\n\n\\begin_layout Subsection\ncmdEnableZifPullups(enable)\n\\end_layout\n\n\\begin_layout Standard\nEnable (True) or disable (False) the pullups for all signals on the ZIF\n socket.\n Default is disabled.\n\\end_layout\n\n\\begin_layout Subsection\ncmdFPGAWrite(address, byte)\n\\end_layout\n\n\\begin_layout Standard\nWrites a byte to the FPGA using \n\\begin_inset Quotes eld\n\\end_inset\n\naddress\n\\begin_inset Quotes erd\n\\end_inset\n\n for address latching and \n\\begin_inset Quotes eld\n\\end_inset\n\nbyte\n\\begin_inset Quotes erd\n\\end_inset\n\n as payload data.\n Note that address 0x10 is fast-tracked and uses one byte less on the USB\n bus.\n So it is potentially faster.\n\\end_layout\n\n\\begin_layout Subsection\ncmdFPGARead(address)\n\\end_layout\n\n\\begin_layout Standard\nReads a byte from the FPGA and puts it into the buffer register.\n \n\\begin_inset Quotes eld\n\\end_inset\n\naddress\n\\begin_inset Quotes erd\n\\end_inset\n\n is used for address latching on the FPGA.\n The microcontroller's buffer register has an automagically incrementing\n pointer.\n So issueing several cmdFPGARead() in a row will result in all the bytes\n being put one after another into the buffer register.\n The buffer register does have a limited size.\n Overflowing it crashes the programmer, requireing a physical USB disconnect\n to recover.\n Call getBufferRegSize() to get the size of the buffer register.\n Reading the buffer register (cmdReadBufferReg()) will reset the automagic\n pointer to zero.\n Note that address 0x10 is fast-tracked and uses one byte less on the USB\n bus.\n So it is potentially faster.\n\\end_layout\n\n\\begin_layout Subsection\ncmdDelay(seconds)\n\\end_layout\n\n\\begin_layout Standard\nSend a delay command to the programmer.\n The Programmer will perform the delay.\n A value up to 0.5 seconds is possible.\n Note that the actual value will be rounded up to the next possible wait\n interval value.\n Use this for short (microsecond or low millisecond) delays.\n Note that this does _not_ flush the command queue.\n\\end_layout\n\n\\begin_layout Subsection\nhostDelay(seconds)\n\\end_layout\n\n\\begin_layout Standard\nSends all queued commands to the device and waits for \n\\begin_inset Quotes eld\n\\end_inset\n\nseconds\n\\begin_inset Quotes erd\n\\end_inset\n\n.\n \n\\begin_inset Quotes eld\n\\end_inset\n\nseconds\n\\begin_inset Quotes erd\n\\end_inset\n\n is a floating point number.\n The delay is performed on the host computer by simply not sending commands\n to the programmer for the time specified after flushing the command queue.\n\\end_layout\n\n\\begin_layout Section\nTX command queueing\n\\end_layout\n\n\\begin_layout Standard\nAll commands transmitted to the device are not sent immediately, but queued\n in software and sent later.\n This is done to speed up device access significantly.\n The command transmission queue has several flushing conditions:\n\\end_layout\n\n\\begin_layout Itemize\nCommands can be flushed explicitely using the \n\\begin_inset Quotes eld\n\\end_inset\n\nflushCommands()\n\\begin_inset Quotes erd\n\\end_inset\n\n method of \n\\begin_inset Quotes eld\n\\end_inset\n\nclass TOP\n\\begin_inset Quotes erd\n\\end_inset\n\n.\n \n\\end_layout\n\n\\begin_layout Itemize\nCommands are automatically flushed on cmdReadBufferReg() before reading\n the data from the device.\n This is to ensure sequential consistency of the commands.\n\\end_layout\n\n\\begin_layout Itemize\nCommands are flushed on various voltage-layout operations.\n\\end_layout\n\n\\begin_layout Standard\nYou usually do not need to flush commands explicitely.\n\\end_layout\n\n\\begin_layout Section\nImplementing a new chip (DUT) algorithm\n\\end_layout\n\n\\begin_layout Standard\nThe reading and programming algorithms for the chips (DUTs) are separated\n into two parts:\n\\end_layout\n\n\\begin_layout Itemize\nLow level FPGA bottom-half\n\\end_layout\n\n\\begin_layout Itemize\nHigh level Python code top-half\n\\end_layout\n\n\\begin_layout Standard\nThe FPGA bottom-half implements the basic operations (fetching data from\n DUT.\n Writing data to DUT.\n etc...).\n It may also implement timingcritical parts of the algorithm.\n Everything else is implemented in the high level Python code, that lives\n on the other end of the USB line.\n\\end_layout\n\n\\begin_layout Subsection\nPython top-half implementation\n\\end_layout\n\n\\begin_layout Standard\nThe DUT specific top-half lives in the \n\\begin_inset Quotes eld\n\\end_inset\n\nlibtoprammer/chips\n\\begin_inset Quotes erd\n\\end_inset\n\n module.\n The files in that module contain the top-half algorithm implementation.\n The files are named after the chip ID.\n Make sure to update the __init__.py of the module when adding algorithm\n implementations.\n The top-half files contain a class derived from the \n\\begin_inset Quotes eld\n\\end_inset\n\nChip\n\\begin_inset Quotes erd\n\\end_inset\n\n class.\n The \n\\begin_inset Quotes eld\n\\end_inset\n\nChip\n\\begin_inset Quotes erd\n\\end_inset\n\n class defines the interface that is to be re-implemented in the derived\n subclass.\n This interface consists of the following methods:\n\\end_layout\n\n\\begin_layout Description\nshutdownChip() Called once on chip shutdown.\n The default implementation turns off all voltages.\n There's usually no need to override that.\n\\end_layout\n\n\\begin_layout Description\nreadSignature() Read the DUT signature and return it.\n Reimplement this, if your DUT supports signature reading.\n\\end_layout\n\n\\begin_layout Description\nerase() Erase the DUT.\n Reimplement this, if your DUT supports electrical erasing.\n\\end_layout\n\n\\begin_layout Description\ntest() Run an optional unit-test on the chip.\n The generic algorithm GenericAlgorithms.simpleTest may be used to implement\n this method.\n\\end_layout\n\n\\begin_layout Description\nreadProgmem() Read the program memory and return it.\n Reimplement this, if your DUT has program memory and supports reading it.\n\\end_layout\n\n\\begin_layout Description\nwriteProgmem(image) Write the program memory.\n Reimplement this, if your DUT has program memory and supports writing it.\n\\end_layout\n\n\\begin_layout Description\nreadEEPROM() Read the (E)EPROM memory and return it.\n Reimplement this, if your DUT has (E)EPROM memory and supports reading\n it.\n\\end_layout\n\n\\begin_layout Description\nwriteEEPROM() Write the (E)EPROM memory.\n Reimplement this, if your DUT has (E)EPROM memory and supports writing\n it.\n\\end_layout\n\n\\begin_layout Description\nreadFuse() Read the Fuse memory and return it.\n Reimplement this, if your DUT has Fuses and supports reading them.\n\\end_layout\n\n\\begin_layout Description\nwriteFuse() Write the Fuse memory.\n Reimplement this, if your DUT has Fuses and supports writing them.\n\\end_layout\n\n\\begin_layout Description\nreadLockbits() Read the Lockbit memory and return it.\n Reimplement this, if your DUT has Lockbits and supports reading them.\n\\end_layout\n\n\\begin_layout Description\nwriteLockbits() Write the Lockbit memory.\n Reimplement this, if your DUT has Lockbits and supports writing them.\n\\end_layout\n\n\\begin_layout Description\nreadRAM() Read the Random Access Memory.\n Reimplement this, if your DUT has RAM and supports reading it.\n\\end_layout\n\n\\begin_layout Description\nwriteRAM() Write the Random Access Memory.\n Reimplement this, if your DUT has RAM and supports writing to it.\n\\end_layout\n\n\\begin_layout Standard\nAfter defining your \n\\begin_inset Quotes eld\n\\end_inset\n\nChip\n\\begin_inset Quotes erd\n\\end_inset\n\n-derived class you need to register it.\n This is done by defining a ChipDescription():\n\\end_layout\n\n\\begin_layout LyX-Code\nChipDescription(Chip_MyDevice, bitfile = \n\\begin_inset Quotes eld\n\\end_inset\n\nbitfileID\n\\begin_inset Quotes erd\n\\end_inset\n\n, chipID = \n\\begin_inset Quotes eld\n\\end_inset\n\nmyChipID\n\\begin_inset Quotes erd\n\\end_inset\n\n)\n\\end_layout\n\n\\begin_layout Standard\nThe chip class (_not_ an instance of it) is passed as first parameter.\n The ID string of the required bitfile is past as second parameter.\n A chipID might also be passed.\n If the chipID is omitted, the bitfileID is used as chipID.\n There are more optional parameters to ChipDescription().\n See the inline sourcecode documentation for details.\n\\end_layout\n\n\\begin_layout Subsection\nGeneric top-half algorithms\n\\end_layout\n\n\\begin_layout Standard\nThe Python class \n\\begin_inset Quotes eld\n\\end_inset\n\nGenericAlgorithms\n\\begin_inset Quotes erd\n\\end_inset\n\n in the generic_algorithms.py file provides several generic chip access algorithm\ns that can be used in the \n\\begin_inset Quotes eld\n\\end_inset\n\nChip\n\\begin_inset Quotes erd\n\\end_inset\n\n methods.\n\\end_layout\n\n\\begin_layout Subsection\nFPGA bottom-half implementation\n\\end_layout\n\n\\begin_layout Standard\nFor the FPGA part you need to get the Xilinx development suite (ISE) version\n 10.1 service pack 3.\n The \"WebPACK\", which is sufficient for our purposes, can be downloaded\n for free (as in beer) from the Xilinx homepage:\n\\end_layout\n\n\\begin_layout LyX-Code\nhttp://www.xilinx.com/support/download/index.htm\n\\end_layout\n\n\\begin_layout Standard\nTo create a new sourcecode template fileset for a new chip, go to the libtopramm\ner/fpga/src/ subdirectory and execute the \"create.sh\" script:\n\\end_layout\n\n\\begin_layout LyX-Code\n./create.sh bitfile_name\n\\end_layout\n\n\\begin_layout Standard\nWhere \"bitfile_name\" is the name of the new chip's bitfile.\n (That often matches the chip-ID).\n Now go to libtoprammer/fpga/src/bitfile_name/ and implement the bottom-half\n algorithm in the bitfile_name.v Verilog file.\n To build the .BIT file from the Verilog sources, go to the libtoprammer/fpga/\n directory and execute:\n\\end_layout\n\n\\begin_layout LyX-Code\n./build.sh bitfile_name\n\\end_layout\n\n\\begin_layout Standard\nIf you omit the \n\\begin_inset Quotes eld\n\\end_inset\n\nbitfile_name\n\\begin_inset Quotes erd\n\\end_inset\n\n, all bitfiles will be rebuilt.\n The resulting .BIT file will be copied to the libtoprammer/fpga/bin/ directory,\n after build finished successfully.\n\\end_layout\n\n\\begin_layout Section\nAutomatic layout generator\n\\end_layout\n\n\\begin_layout Standard\nThe automatic layout generator (layout_generator.py) can be used to automatically\n generate a VCC/VPP/GND layout.\n The generator will then tell you how to insert the chip into the ZIF socket.\n The advantage of using the autogenerator instead of hardcoding the VCC/VPP/GND\n connections in the chip implementation is that the autogenerated layout\n is portable between TOPxxxx programmers and it is much easier to implement.\n You do not have to search for a chip position in the ZIF socket that fits\n the device constraints.\n The autogenerator will do it for you.\n\\end_layout\n\n\\begin_layout Standard\nThe chip interface of the autogenerator is embedded into \n\\begin_inset Quotes eld\n\\end_inset\n\nclass Chip\n\\begin_inset Quotes erd\n\\end_inset\n\n.\n So you don't have to work with \n\\begin_inset Quotes eld\n\\end_inset\n\nclass LayoutGenerator\n\\begin_inset Quotes erd\n\\end_inset\n\n directly.\n You'll do it through \n\\begin_inset Quotes eld\n\\end_inset\n\nclass Chip\n\\begin_inset Quotes erd\n\\end_inset\n\n instead.\n So let's look at \n\\begin_inset Quotes eld\n\\end_inset\n\nclass Chip\n\\begin_inset Quotes erd\n\\end_inset\n\ns autogenerator interface.\n\\end_layout\n\n\\begin_layout Standard\nThe constructor (__init__()) has some autogenerator related parameters:\n\\end_layout\n\n\\begin_layout Description\nchipPackage This parameter is a string identifying the package type of the\n DUT chip.\n It is something like \n\\begin_inset Quotes eld\n\\end_inset\n\nDIP28\n\\begin_inset Quotes erd\n\\end_inset\n\n or \n\\begin_inset Quotes eld\n\\end_inset\n\nDIP40\n\\begin_inset Quotes erd\n\\end_inset\n\n, etc...\n .\n If this parameter is passed to the constructor, the autogenerator is enabled.\n\\end_layout\n\n\\begin_layout Description\nchipPinVCC This parameter is an integer specifying the VCC pin on the chip\n package.\n Note that it specifies the VCC pin on the chip package and _not_ on the\n ZIF socket.\n So if your chip datasheet tells you that VCC is on pin 8, you pass an 8\n here.\n\\end_layout\n\n\\begin_layout Description\nchipPinsVPP This parameter is an integer or a list of integers specifying\n the VPP pin(s) on the chip package.\n Note that it specifies the VPP pin on the chip package and _not_ on the\n ZIF socket.\n So if your chip datasheet tells you that VPP is on pin 1, you pass a 1\n here.\n If your chip needs multiple VPP voltages, just pass a list of pins.\n Specify all possible VPP pins here.\n Which pin is actually activated is decided later in applyVPP().\n\\end_layout\n\n\\begin_layout Description\nchipPinGND This parameter is an integer specifying the GND pin on the chip\n package.\n Note that it specifies the GND pin on the chip package and _not_ on the\n ZIF socket.\n So if your chip datasheet tells you that GND is on pin 5, you pass a 5\n here.\n\\end_layout\n\n\\begin_layout Standard\nAfter passing all parameters to the \n\\begin_inset Quotes eld\n\\end_inset\n\nclass Chip\n\\begin_inset Quotes erd\n\\end_inset\n\n constructor, the autogenerator is initialized and ready to be used.\n The following \n\\begin_inset Quotes eld\n\\end_inset\n\nclass Chip\n\\begin_inset Quotes erd\n\\end_inset\n\n methods can be used to enable or disable a layout:\n\\end_layout\n\n\\begin_layout Description\napplyVCC(on) This method enables or disables (depending on the \n\\begin_inset Quotes eld\n\\end_inset\n\non\n\\begin_inset Quotes erd\n\\end_inset\n\n parameter) the VCC layout.\n Enabling the layout means that the VCC pin will be actively driven by the\n configured VCC voltage.\n Disabling the layout will tristate the driver.\n\\end_layout\n\n\\begin_layout Description\napplyVPP(on,packagePinsToTurnOn) This method enables or disables (depending\n on the \n\\begin_inset Quotes eld\n\\end_inset\n\non\n\\begin_inset Quotes erd\n\\end_inset\n\n parameter) the VPP layout.\n Enabling the layout means that the VPP pins will be actively driven by\n the configured VPP voltage.\n Disabling the layout will tristate the driver.\n The first parameter \n\\begin_inset Quotes eld\n\\end_inset\n\non\n\\begin_inset Quotes erd\n\\end_inset\n\n is a boolean to turn ON or OFF the VPP layout.\n The second parameter is an optional list of package-pin-numbers specifying\n which VPP is turned on.\n If the second parameter is not passed, all possible VPPs that were specified\n in the constructor are turned on.\n The second parameter is unused, if \n\\begin_inset Quotes eld\n\\end_inset\n\non=False\n\\begin_inset Quotes erd\n\\end_inset\n\n.\n\\end_layout\n\n\\begin_layout Description\napplyGND(on) This method enables or disables (depending on the \n\\begin_inset Quotes eld\n\\end_inset\n\non\n\\begin_inset Quotes erd\n\\end_inset\n\n parameter) the GND layout.\n Enabling the layout means that the GND pins will be actively driven by\n GND.\n Disabling the layout will tristate the driver.\n\\end_layout\n\n\\end_body\n\\end_document\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmbuesch%2Ftoprammer","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmbuesch%2Ftoprammer","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmbuesch%2Ftoprammer/lists"}