{"id":19206708,"url":"https://github.com/mcquerol/vhdl-projects","last_synced_at":"2026-03-19T08:42:35.232Z","repository":{"id":191207024,"uuid":"683468353","full_name":"mcquerol/vhdl-projects","owner":"mcquerol","description":"VHDL projects for combinational and sequential logic design on FPGA.","archived":false,"fork":false,"pushed_at":"2024-12-18T01:22:36.000Z","size":173,"stargazers_count":2,"open_issues_count":2,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-07-12T01:32:55.525Z","etag":null,"topics":["combinational-logic","flip-flops","latches","logisim","memory","sequential-logic","vhdl"],"latest_commit_sha":null,"homepage":null,"language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mcquerol.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-08-26T17:06:55.000Z","updated_at":"2025-04-23T19:24:15.000Z","dependencies_parsed_at":"2023-08-28T20:18:23.231Z","dependency_job_id":"d28bfda2-48a4-4cb0-ab83-51235428ccea","html_url":"https://github.com/mcquerol/vhdl-projects","commit_stats":null,"previous_names":["mcquerol/vhdl-projects"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/mcquerol/vhdl-projects","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mcquerol%2Fvhdl-projects","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mcquerol%2Fvhdl-projects/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mcquerol%2Fvhdl-projects/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mcquerol%2Fvhdl-projects/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mcquerol","download_url":"https://codeload.github.com/mcquerol/vhdl-projects/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mcquerol%2Fvhdl-projects/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29844845,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-25T22:37:40.667Z","status":"ssl_error","status_checked_at":"2026-02-25T22:37:25.960Z","response_time":61,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["combinational-logic","flip-flops","latches","logisim","memory","sequential-logic","vhdl"],"created_at":"2024-11-09T13:16:42.346Z","updated_at":"2026-02-25T23:06:03.999Z","avatar_url":"https://github.com/mcquerol.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# vhdl-projects\n\nThis is a standard README file for the vhdl-projects repository.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmcquerol%2Fvhdl-projects","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmcquerol%2Fvhdl-projects","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmcquerol%2Fvhdl-projects/lists"}