{"id":19178778,"url":"https://github.com/meetps/ee-214","last_synced_at":"2026-02-28T12:42:03.516Z","repository":{"id":26833712,"uuid":"30293023","full_name":"meetps/EE-214","owner":"meetps","description":"VHDL and Verilog Codes for Digital Lab.","archived":false,"fork":false,"pushed_at":"2015-06-11T05:57:43.000Z","size":3733,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-02-23T01:34:54.201Z","etag":null,"topics":["digital-logic","fpga","verilog","vhdl"],"latest_commit_sha":null,"homepage":null,"language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/meetps.png","metadata":{},"created_at":"2015-02-04T10:14:32.000Z","updated_at":"2023-02-02T20:07:14.000Z","dependencies_parsed_at":"2022-09-01T19:00:47.476Z","dependency_job_id":null,"html_url":"https://github.com/meetps/EE-214","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/meetps/EE-214","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meetps%2FEE-214","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meetps%2FEE-214/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meetps%2FEE-214/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meetps%2FEE-214/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/meetps","download_url":"https://codeload.github.com/meetps/EE-214/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meetps%2FEE-214/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29934447,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-28T12:34:16.884Z","status":"ssl_error","status_checked_at":"2026-02-28T12:34:13.721Z","response_time":90,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["digital-logic","fpga","verilog","vhdl"],"created_at":"2024-11-09T10:40:54.169Z","updated_at":"2026-02-28T12:42:03.506Z","avatar_url":"https://github.com/meetps.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":null,"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmeetps%2Fee-214","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmeetps%2Fee-214","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmeetps%2Fee-214/lists"}