{"id":26406230,"url":"https://github.com/mehedi-86/logisim_projects","last_synced_at":"2026-02-18T15:01:02.631Z","repository":{"id":281203375,"uuid":"944540208","full_name":"Mehedi-86/Logisim_Projects","owner":"Mehedi-86","description":"This repository includes Logisim Evolution circuits for a 3-Bit Down Counter, BCD to Excess-3 Converter, BCD to Hex Display, 4-Bit Comparator, and Cache Memory, covering sequential logic, number conversions, and memory design. 🚀","archived":false,"fork":false,"pushed_at":"2025-03-07T14:37:52.000Z","size":787,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-10-11T00:38:35.968Z","etag":null,"topics":["3-bit-down-counter","4-bit-comparator","bcd-to-7-segment","bcd-to-excess-3-convertor","cache-memory","logisim-circuit","logisim-evolution"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Mehedi-86.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2025-03-07T14:26:21.000Z","updated_at":"2025-03-07T14:49:36.000Z","dependencies_parsed_at":"2025-03-07T15:42:57.458Z","dependency_job_id":null,"html_url":"https://github.com/Mehedi-86/Logisim_Projects","commit_stats":null,"previous_names":["mehedi-86/logisim_projects"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/Mehedi-86/Logisim_Projects","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mehedi-86%2FLogisim_Projects","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mehedi-86%2FLogisim_Projects/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mehedi-86%2FLogisim_Projects/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mehedi-86%2FLogisim_Projects/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Mehedi-86","download_url":"https://codeload.github.com/Mehedi-86/Logisim_Projects/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mehedi-86%2FLogisim_Projects/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29582786,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-18T13:56:48.962Z","status":"ssl_error","status_checked_at":"2026-02-18T13:54:34.145Z","response_time":162,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["3-bit-down-counter","4-bit-comparator","bcd-to-7-segment","bcd-to-excess-3-convertor","cache-memory","logisim-circuit","logisim-evolution"],"created_at":"2025-03-17T17:18:52.321Z","updated_at":"2026-02-18T15:01:02.411Z","avatar_url":"https://github.com/Mehedi-86.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"# 🚀 Logisim Projects\n\n## 📖 Introduction\nThis repository contains multiple **digital logic circuits** implemented using **Logisim Evolution**. These circuits demonstrate fundamental concepts of digital electronics, such as counters, arithmetic operations, encoding/decoding, and memory organization. Each project focuses on a specific functionality and showcases how digital components interact to perform various logical operations.\n\n## 🛠 Included Circuits\n\n### 1️⃣ **3-Bit Down Counter**\nA synchronous **3-bit down counter** that counts in descending order (7 → 6 → 5 → ... → 0 → 7). It utilizes **flip-flops, clock signals,** and **reset logic** to decrement the count at every clock pulse.\n\n**Key Features:**\n- Uses **D or T flip-flops** to store binary count values.\n- Decrements the count on every clock pulse.\n- Implements **asynchronous/synchronous reset** for proper initialization.\n- Can be extended to larger bit-widths as needed.\n\n### 2️⃣ **BCD to Excess-3 Converter**\nThis circuit converts a **Binary-Coded Decimal (BCD)** number to its equivalent **Excess-3 (XS-3)** representation. Excess-3 encoding is commonly used in digital systems and arithmetic circuits.\n\n**Key Features:**\n- Implements **binary addition logic** to add '3' to the BCD input.\n- Uses combinational logic gates for efficient conversion.\n- Avoids invalid BCD states, ensuring correct representation.\n\n### 3️⃣ **BCD to Hex 7-Segment Display Decoder**\nA digital circuit that converts a **4-bit BCD input** into a **7-segment display format**, allowing numerical values (0-9) and hexadecimal values (A-F) to be displayed correctly.\n\n**Key Features:**\n- Uses combinational logic to generate **7-segment display outputs**.\n- Implements **truth tables** for proper character mapping.\n- Supports **both numerical (0-9) and hexadecimal (A-F) digits**.\n\n### 4️⃣ **4-Bit Comparator**\nA **4-bit magnitude comparator** that compares two **4-bit binary numbers (A and B)** and determines their relationship: greater than, less than, or equal.\n\n**Key Features:**\n- Outputs **A \u003e B, A \u003c B, and A = B** conditions.\n- Uses combinational logic circuits like **AND, OR, NOT, XOR gates**.\n- Can be extended to compare larger bit-widths by cascading multiple units.\n\n### 5️⃣ **Cache Memory Simulation (2107086_Cache.circ)**\nA **basic cache memory simulation** that demonstrates how cache storage works in a digital system. This project showcases **cache hits, misses, and data retrieval processes**.\n\n**Key Features:**\n- Implements **direct-mapped or associative cache logic**.\n- Simulates memory access patterns to observe **cache performance**.\n- Uses **RAM/ROM components** to store frequently accessed data.\n\n## 📂 File Structure\n```plaintext\n/Logisim_Projects\n│── 3 bit downcounter.circ  # Synchronous 3-bit down counter\n│── BCD to Excess 3 circuit 2107086.circ  # BCD to Excess-3 converter\n│── BCD to Hex 7 segment circuit 2107086.circ  # BCD to 7-segment decoder\n│── 4 bit comparator 2107086.circ  # 4-bit binary comparator\n│── 2107086_Cache.circ  # Cache memory simulation\n│── README.md  # Documentation file\n```\n\n## 🚀 How to Run the Circuits\n\n### 🔹 Steps to Open in Logisim Evolution\n1. **Download and Install** Logisim Evolution → [Logisim Evolution](https://logisim-evolution.org)\n2. **Open Logisim Evolution** and load the desired circuit file.\n3. **Start the Simulation** by clicking **Simulate → Tick Once** or enabling continuous ticking.\n4. **Modify Inputs and Observe Outputs** using switches and LEDs.\n\n## 🔍 Debugging \u0026 Common Issues\n\n### 🔹 Floating Inputs (Red Wires)\n- Ensure all inputs have defined values (**use constants or input switches**).\n- Verify correct connections in combinational circuits.\n\n### 🔹 Incorrect Outputs\n- Check **flip-flop connections** in sequential circuits.\n- Verify **truth tables** for combinational logic correctness.\n- Ensure proper clock signals are applied.\n\n## 🛠 Future Improvements\n- ✅ Extend counter circuits to **higher bit-widths**.\n- ✅ Implement **priority encoders and decoders**.\n- ✅ Improve **cache replacement strategies** for better performance.\n\n## 📜 License\nThis project is **open-source**. Feel free to use, modify, and contribute!\n\n## 💡 Conclusion\nThis repository serves as a practical guide to **digital logic design** using **Logisim Evolution**. Each project highlights core **digital electronics concepts**, making it useful for students and hobbyists exploring **computer architecture and circuit design**.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmehedi-86%2Flogisim_projects","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmehedi-86%2Flogisim_projects","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmehedi-86%2Flogisim_projects/lists"}