{"id":24550867,"url":"https://github.com/meiniki/fazyrv","last_synced_at":"2026-01-04T03:03:19.981Z","repository":{"id":225120004,"uuid":"760114130","full_name":"meiniKi/FazyRV","owner":"meiniKi","description":"A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.","archived":false,"fork":false,"pushed_at":"2024-09-04T10:07:50.000Z","size":791,"stargazers_count":77,"open_issues_count":0,"forks_count":4,"subscribers_count":7,"default_branch":"main","last_synced_at":"2025-01-23T01:14:43.998Z","etag":null,"topics":["computer-architecture","digital-design","embedded-systems","fpga","risc-v","system-on-chip","vlsi-design"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/meiniKi.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-02-19T20:09:47.000Z","updated_at":"2025-01-03T08:21:24.000Z","dependencies_parsed_at":"2024-03-07T13:37:43.272Z","dependency_job_id":"f4749460-463e-444d-9e37-8675fbc76fed","html_url":"https://github.com/meiniKi/FazyRV","commit_stats":null,"previous_names":["meiniki/fazyrv"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meiniKi%2FFazyRV","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meiniKi%2FFazyRV/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meiniKi%2FFazyRV/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meiniKi%2FFazyRV/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/meiniKi","download_url":"https://codeload.github.com/meiniKi/FazyRV/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243874173,"owners_count":20361778,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["computer-architecture","digital-design","embedded-systems","fpga","risc-v","system-on-chip","vlsi-design"],"created_at":"2025-01-23T01:14:49.299Z","updated_at":"2026-01-04T03:03:19.907Z","avatar_url":"https://github.com/meiniKi.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"\u003cimg align=\"right\" src=\"doc/logos/fazyrv.svg\" alt=\"Spacing\" width=\"18%\" height=\"18%\"\u003e\n\n# FazyRV -- A Scalable RISC-V Core\n\nA minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.\n\n## Table of Content\n- [FazyRV -- A Scalable RISC-V Core](#fazyrv----a-scalable-risc-v-core)\n  - [Table of Content](#table-of-content)\n  - [Introduction](#introduction)\n    - [Area / Resource Demand](#area--resource-demand)\n    - [Organization](#organization)\n    - [Acknowledgement](#acknowledgement)\n  - [Design Variants](#design-variants)\n  - [Quick Start](#quick-start)\n    - [Prepare the Environment](#prepare-the-environment)\n    - [Reference SoC](#reference-soc)\n    - [Litex](#litex)\n  - [Tests and Verification](#tests-and-verification)\n    - [Run riscv-tests](#run-riscv-tests)\n    - [Run RISCOF](#run-riscof)\n    - [Module-Level Formal Checks](#module-level-formal-checks)\n    - [riscv-formal](#riscv-formal)\n  - [Benchmarks](#benchmarks)\n    - [Embench](#embench)\n  - [Decoder](#decoder)\n  - [Related Resources and Further Readings](#related-resources-and-further-readings)\n  - [TODOs](#todos)\n  - [Licensing](#licensing)\n\n## Introduction\n\nFazyRV is a minimal-area RISC-V RV32 core with inherent scalability. The data path can be set to a width of either 1, 2, 4, or 8 bits to process smaller _chunks_ of the operands each clock cycle. Scaling the chunk size allows a trade-off between area and performance at synthesis time. Moreover, each chunk size can be combined with manifold variants to find the best-fitting configuration and trade-off for given system requirements and technology. In contrast to other approaches, FazyRV tries to avoid manual optimization at the gate level (see also [Decoder](#decoder)).\n\n### Area / Resource Demand\n\nThe plot below tracks the resource demand of the FazyRV core (left) and a minimal reference SoC (right) for an iCE40 architecture. Note that only a few variants are plotted for brevity.\n\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"./doc/area.svg\" alt=\"FazyRV and fsoc areas\"/\u003e\n\u003c/p\u003e\n\n### Organization\n\nFazyRV is contained in `rtl` and licensed under a permissive MIT license.\n`rtl/fazyrv_top.sv` is the top module and instantiates the FazyRV core (`rtl/fazyrv_core.sv`) alongside the register file. The reference SoC (fsoc) is located in `soc/rtl` along with a constraint file for common architectures.\n\n\n\nThe data flow through the core can be outlined as follows:\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"./doc/block.png\" alt=\"block diagram\" style=\"width:550px;\"/\u003e\n\u003c/p\u003e\n\n\n### Acknowledgement\n\n\u003cp\u003e\n  \u003cimg align=\"right\" src=\"doc/logos/tugraz.png\" alt=\"TU Graz Logo\" width=\"14%\" height=\"14%\"\u003e\n  \u003cimg align=\"right\" src=\"doc/logos/spacing.png\" alt=\"Spacing\" width=\"1%\" height=\"1%\"\u003e\n  \u003cimg align=\"right\" src=\"doc/logos/eas.png\" alt=\"EAS Logo\" width=\"8%\" height=\"8%\"\u003e\n\u003c/p\u003e\n\n\nThis repository includes results of research in the [Embedded Architectures \u0026 Systems](https://iti.tugraz.at/eas) (EAS) Group at [Graz University of Technology](https://www.tugraz.at). \n\n\u0026nbsp;\n\n## Design Variants\n\n`CHUNKSIZE` sets the data path width of FazyRV and, thus, primarily determines the required Cycles per Instruction (CPI). When the chunk size is set to 1, a single bit is processed per clock cycle, and an addition, e.g., requires 32 cycles (without fetch and decode) to process the operands. It reduces to 4 clock cycles when 8 bits are processed simultaneously, i.e., `CHUNKSIZE = 8`. The latter variant, however, comes with an increased area demand.\n\n```\nCHUNKSIZE   := 1 | 2 | 4 | 8\n```\n\nThe configuration (`CONF`) determines the functionality of the core. In the `MIN` variant, no interrupts are supported and the core implements to the minimal area achievable. The work-in-progress `INT` variant adds basic interrupt support but sacrifices many features in favor of reduced area. Thus, e.g., `mtvec` can only be set at synthesis time. Finally, the work-in-progress `CSR` variant adds more CSR registers and allows reading and writing them. However, there are deviations from the specification as area remains a main optimization objective.\n\n```\nCONF        := MIN | INT | CSR\n```\n\nThe register file type (`RFTYPE`) influences both the area and the performance. It selects how registers are implemented in FazyRV. The most area-intensive option is `LOGIC`. It implements the registers in logic elements such as LUT RAM or FF RAM. Due to the large area, this option is primarily used for testing purposes and _cannot_ be combined with all variants. `BRAM` implements the register file in block RAM with a single read port. Thus, operands must be fetched sequentially, leading to a performance decrease compared to a dual-port RAM implementation (`BRAM_DP`). The `BP` variants `BRAM_BP` and `BRAM_DP_BP` additionally instantiate a bypass multiplexer to make the operands accessible to the core one cycle in advance. While this improves the performance due to the saved clock cycle per instruction, more area may be consumed.\n\n```\nRFTYPE      := LOGIC | BRAM | BRAM_BP | BRAM_DP | BRAM_DP_BP\n```\n\nIn the default configuration, FazyRV interfaces the memory with a Wishbone interface. `MEMDLY1` allows deviation from the handshake and assumes that each access is directly granted with a one-clock cycle delay until the access is completed and the results are available. This can lower the average CPI when the design ensures the above conditions are met, e.g., when the memory is implemented in BRAM.\n\n```\nMEMDLY1     := 0 | 1\n```\n\n\u003e [!IMPORTANT]  \n\u003e Please note that the core still needs to become production-ready. As there is a strong focus on area, the implemented features in the `INT` and `CSR` variants and allowed deviations from the specification must be carefully considered. Also, note that the `LOGIC` variant is explicitly not considered with `INT` and `CSR` variants. \n\n## Quick Start\n\n### Prepare the Environment\n\nYou may want to use a Python virtual environment. \n\n```shell\npython3 -m venv .venv\nsource .venv/bin/activate\npip install -r requirements.txt\n```\n\n### Reference SoC\n\nfsoc (`soc/fsoc`) is a minimal SoC used to track the core's area demand and run simulation-based tests and benchmarks. The Make targets for the reference implementations are based fusesoc (for most FPGA architectures). `fazyrv.core` and `fsoc.core` core files for FazyRV and fsoc, respectively.\n\nStart by adding core files to the fusesoc library.\n\n```shell\nfusesoc library add fazyrv .\nfusesoc library add fsoc .\n```\n\nThen, you can use the targets in the core file or run the flow with the Make targets below. A reference implementation for the following architectures is supported. Replace `\u003cARCH\u003e` with the desired target architecture (see below). Also, replace `\u003cCHUNKSIZE\u003e`, `\u003cCONF\u003e`, and `\u003cRFTYPE\u003e` with the desired values.\n\n```\nARCH        := ice40 | ecp5 | gowin | xilinx | gatemate\n```\n\n```shell\n# run the flow only\nmake _impl.soc.\u003cARCH\u003e-\u003cCHUNKSIZE\u003e-\u003cCONF\u003e-\u003cRFTYPE\u003e\n\n# run the flow and report a summary of the results\nmake _report.soc.\u003cARCH\u003e-\u003cCHUNKSIZE\u003e-\u003cCONF\u003e-\u003cRFTYPE\u003e\n\n# e.g.,\nmake _report.soc.ice40-8-MIN-BRAM\n\n# or \nmake report.soc.all\n```\n\n### Litex\n\n[LiteX](https://github.com/enjoy-digital/litex) supports FazyRV with the following options: `--cpu-chunksize` to set the chunk size (`1`, `2`, `4`, or `8`), `--cpu-conf` to set the configuration (`MIN`, `INT`, or `CSR`) and `--cpu-rftype` to set the register file type (`LOGIC`, `BRAM`, `BRAM_BP`, `BRAM_DP`, or `BRAM_DP_BP`).\n\n```shell\nlitex_sim --cpu-type=fazyrv --cpu-chunksize=4 --cpu-rftype=LOGIC\n```\n\n## Tests and Verification\n\n### Run riscv-tests\n\nriscv-tests are used as fast checks to get feedback if a variant is broken. However, the tests are not as sensitive as the RISCOF tests and may report false positives.\n\nExecute the tests with the make target below by replacing the `\u003cCHUNKSIZE\u003e`, `\u003cCONF\u003e`, and `\u003cRFTYPE\u003e` with the desired variant or run it on all variants.\n\n```shell\n# riscv-tests\nmake sim.riscvtests.\u003cCHUNKSIZE\u003e-\u003cCONF\u003e-\u003cRFTYPE\u003e\n# e.g.,\nmake sim.riscvtests.8-MIN-BRAM\n# or\nmake report.riscvtests.all\n```\n\n\n### Run RISCOF\n\nThe RISCOF framework provides more extensive simulation-based design tests. You can run the test either for one variant or use `riscof.all` to run  the tests for a selected subset of all variants.\n\n```shell\n# RISCOF\nmake riscof.prepare\nmake riscof.run.\u003cCHUNKSIZE\u003e-\u003cCONF\u003e-\u003cRFTYPE\u003e\n# e.g.,\nmake riscof.prepare\nmake riscof.run.8-MIN-BRAM\n# or\nmake riscof.prepare\nmake riscof.all\n```\n\n### Module-Level Formal Checks\nThe ALU (`rtl/fazyrv_alu.sv`) and the `spm_d` module (`rtl/fazyrv_spm_d.sv`) are checked by BMC in a formal test bench. The test benches and `.sby` files are located in `fv/alu` and `fv/spm_d`, respectively. These were primarily used to support a formal verification test-driven development when the core was not ready to be checked by `riscv-formal`. However, they remain important to verify changes and optimizations. The chunk size is set to 8 by default. If required, please update the local parameter `parameter CHUNKSIZE` in the formal test benches accordingly.\n\n```shell\n# alu\ncd fv/alu\nsby -f fazyrv_alu_bmc.sby\nsby -f fazyrv_alu_cov.sby\n\n# spm_d\ncd fv/spm_d\nsby -f fazyrv_spm_d_bmc.sby\nsby -f fazyrv_spm_d_cov.sby\n```\n\n### riscv-formal\n\nIn addition to simulation-based tests, formal checks are applied using riscv-formal. Due to the exponential run time, formal checks are primarily considered for larger chunk sizes. Also, the depth is limited. \n\n```shell\n# insn checks\nmake fv.rvformal.bmc.insn.\u003cCHUNKSIZE\u003e\nmake fv.rvformal.cov.insn.\u003cCHUNKSIZE\u003e\n\n# reg checks\nmake fv.rvformal.bmc.reg.\u003cCHUNKSIZE\u003e\nmake fv.rvformal.cov.reg.\u003cCHUNKSIZE\u003e\n\n# e.g.\nmake fv.rvformal.bmc.insn.8 \u0026\u0026 make fv.rvformal.cov.insn.8\n\n# or run them sequentiall on all chunk sizes\nmake fv.rvformal.bmc.insn.al\nmake fv.rvformal.bmc.reg.all\nmake fv.rvformal.cov.insn.all\nmake fv.rvformal.cov.reg.all\n```\n\n## Benchmarks\n\n### Embench\n\nEmbench is used to benchmark FazyRV and compare it to similar minimal-area cores. It can be run via a Make target.\n\n```shell\nmake embench.run\n```\n\nThe target calls the shell script `script/benchmark_run_embench_all.sh`. Please adapt it to run the benchmark suite on the desired variants. `--insn_timing` is used to store information about all executed instructions on the disk. It can be used to analyze and compare the cycles per instructions (CPI). Note that this significantly increases the required disk space.\n\n\n## Decoder\n\nFazyRV is written at a Verilog RTL abstraction level that remains human-readable. Thus, hand-optimization at the gate level is avoided whenever possible. However, some parts of the design benefit from optimization at a lower level, such as the combinational logic in the instruction decoder. Thus, the decoder is given in a table-like format that can be fed into the ESPRESSO logic optimizer to generate an optimized gate-level description. The input file (`optimizer/decoder/decoder`) can be edited efficiently. The instruction bits can either be checked explicitly or set to _don't care_ when they are not required to interpret legal instructions. The former has more freedom to optimize to a smaller implementation but is more insecure when illegal instructions appear.\n\n```shell\nespresso -o eqntott -Dso_both ~/Documents/public_repos/FazyRV/optimizer/decoder/decoder \u003e tmp\n```\n\nThe output gate-level Verilog code can then be updated in the decoder implementation (`rtl/fazyrv_decode.sv`).\n\nA simple fuzzing script is used to estimate the optimization potential of the decoder. It iteratively sets bits to _don't care_ and tests the modification. First, riscv-tests are run to find broken decoders quickly and shorten the overall run time. When the riscv-tests pass, a riscv-formal formal verification run is started on the insn checks for the 8-bit variant. Then, the modification is either reverted or the _don't care_ is kept. The fuzzer is **solely for testing purposes**. It is _not_ recommended to take over the optimized result. The final decoder must be carefully checked and thoroughly verified on all variants before using it in the core. Please note that the current version only tests one bit at a time and may be improved.\n\n```shell\ncd optimizer/decoder/decode_opt\npython3 fuzz.py --espresso_file ../decoder --riscvtests_dir ../../../sim --riscvformal_dir ../../../ --template_verilog fazyrv_decode.template --template_marker \"//\u003cPUT_IT_HERE\u003e\" --destination_verilog ../../../rtl/fazyrv_decode.sv --espresso_optimized espresso.optimized\n```\n\n## Related Resources and Further Readings\n\n* We presented this work at the 21st ACM International Conference on Computing Frontiers (CF '24). You can find the [paper here](https://dl.acm.org/doi/10.1145/3649153.3649195) (open access). It summarizes our design objectives, gives insight into the design and trade-offs, compares similar cores, and provides an in-depth evaluation.\n\nPlease cite the work as follows:\n\n```\n@inproceedings{fazyrv2024kissich,\n  title = {{FazyRV: Closing the Gap between 32-Bit and Bit-Serial RISC-V Cores with a Scalable Implementation}},\n  booktitle = {Proc. of the 21st ACM International Conference on Computing Frontiers (CF ’24)},\n  author = {Kissich, Meinhard and Baunach, Marcel},\n  year = {2024},\n  month = {May},\n  publisher = {Association for Computing Machinery},\n  url = {https://doi.org/10.1145/3649153.3649195},\n  doi = {10.1145/3649153.3649195},\n  booktitle = {Proceedings of the 21st ACM International Conference on Computing Frontiers},\n  pages = {240–248}\n}\n```\n\n* [FazyRV-ExoTiny](https://github.com/meiniKi/FazyRV-ExoTiny) is a SoC built around FazyRV, focusing on minimizing the added area. It uses external QSPI instruction memory (flash) and external QSPI RAM.\n\n* [tt06-FazyRV-ExoTiny](https://github.com/meiniKi/tt06-FazyRV-ExoTiny) is a [TinyTypeout](https://tinytapeout.com/runs/tt06/462/) based on [FazyRV-ExoTiny](https://github.com/meiniKi/FazyRV-ExoTiny).\n\n* Do you want to see how powerful bit-serial cores are? Check out our [demonstrator](https://www.linkedin.com/posts/meinhard-kissich-43b19812a_think-bit-serial-risc-v-cores-lack-power-activity-7192074324109926400-ZOwL?utm_source=share\u0026utm_medium=member_desktop) running a port of the Arduboy gaming framework.\n\n* YosysHQ invited us to contribute a blog post. Check out [our FazyRV community-spotlight blog post](https://blog.yosyshq.com/p/community-spotlight-fazyrv) and all the [amazing open-source projects](https://blog.yosyshq.com).\n\n\n\n\n## TODOs\n\n- [ ] Workflow: caching, tool versions, artifacts, dependence on some local tools\n- [ ] RVC extension (compressed instructions)\n- [ ] INT variant\n- [ ] CSR variant\n- [ ] CSR instructions in addition to `csrrw`(?)\n- [ ] Use edalize reporting instead of custom scripts\n- [ ] Optimization\n- [ ] More documentation\n\nPlease feel free to discuss and open an issue and/or pull request.\n\n## Licensing\n\nThe FazyRV core (`rtl/*`) is licensed under the MIT license. This license may _not_ apply to the remainder of the repository.","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmeiniki%2Ffazyrv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmeiniki%2Ffazyrv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmeiniki%2Ffazyrv/lists"}