{"id":24550868,"url":"https://github.com/meiniki/rv32i_sc_logisim","last_synced_at":"2026-01-03T07:15:27.905Z","repository":{"id":166630229,"uuid":"515922124","full_name":"meiniKi/RV32I_SC_Logisim","owner":"meiniKi","description":"A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.","archived":false,"fork":false,"pushed_at":"2023-05-17T21:51:07.000Z","size":724,"stargazers_count":3,"open_issues_count":0,"forks_count":0,"subscribers_count":3,"default_branch":"main","last_synced_at":"2025-01-23T01:14:44.864Z","etag":null,"topics":["computer-science","digital-design","educational","logisim","logisim-evolution","processor-architecture","risc-v"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/meiniKi.png","metadata":{},"created_at":"2022-07-20T09:45:17.000Z","updated_at":"2024-12-12T22:47:49.000Z","dependencies_parsed_at":"2023-07-26T11:46:44.803Z","dependency_job_id":null,"html_url":"https://github.com/meiniKi/RV32I_SC_Logisim","commit_stats":null,"previous_names":["meiniki/rv32i_sc_logisim"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meiniKi%2FRV32I_SC_Logisim","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meiniKi%2FRV32I_SC_Logisim/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meiniKi%2FRV32I_SC_Logisim/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/meiniKi%2FRV32I_SC_Logisim/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/meiniKi","download_url":"https://codeload.github.com/meiniKi/RV32I_SC_Logisim/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243874173,"owners_count":20361778,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["computer-science","digital-design","educational","logisim","logisim-evolution","processor-architecture","risc-v"],"created_at":"2025-01-23T01:14:49.308Z","updated_at":"2026-01-03T07:15:27.880Z","avatar_url":"https://github.com/meiniKi.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":null,"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmeiniki%2Frv32i_sc_logisim","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmeiniki%2Frv32i_sc_logisim","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmeiniki%2Frv32i_sc_logisim/lists"}