{"id":19410846,"url":"https://github.com/melvinmo/hdl_course_archive","last_synced_at":"2026-02-22T21:40:18.873Z","repository":{"id":191560591,"uuid":"684912213","full_name":"MelvinMo/HDL_Course_Archive","owner":"MelvinMo","description":"This repository houses my work from the undergraduate hardware description language course in Verilog and the utilization of tools such as ModelSim and Xilinx ISE.","archived":false,"fork":false,"pushed_at":"2023-08-30T06:11:16.000Z","size":2318,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-01-07T15:16:59.328Z","etag":null,"topics":["fpga","modelsim","verilog-hdl","xilinx-ise"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/MelvinMo.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null}},"created_at":"2023-08-30T05:27:29.000Z","updated_at":"2023-09-02T16:03:45.000Z","dependencies_parsed_at":null,"dependency_job_id":"992f854e-a2d0-493e-a4b6-0e2b99beeb35","html_url":"https://github.com/MelvinMo/HDL_Course_Archive","commit_stats":null,"previous_names":["melvinmo/hdl_archive","melvinmo/hdl_course_archive"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MelvinMo%2FHDL_Course_Archive","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MelvinMo%2FHDL_Course_Archive/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MelvinMo%2FHDL_Course_Archive/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MelvinMo%2FHDL_Course_Archive/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/MelvinMo","download_url":"https://codeload.github.com/MelvinMo/HDL_Course_Archive/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":240588719,"owners_count":19825224,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","modelsim","verilog-hdl","xilinx-ise"],"created_at":"2024-11-10T12:18:18.263Z","updated_at":"2025-10-29T19:38:47.024Z","avatar_url":"https://github.com/MelvinMo.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# HDL_Archive\nThis repository houses my works from the undergraduate hardware description language course, demonstrating proficiency in Verilog and utilization of industry-standard tools such as ModelSim and Xilinx ISE.\n## Assignment 1\nThis assignment involved designing and testing a sequential logic circuit using Verilog HDL. The objective was to gain hands-on experience in digital circuit design, Verilog modeling, and functional verification using ModelSim.\n## Assignment 2\nThe goal was to enhance skills in structural modeling and test bench automation. I designed a 4-bit binary comparator in Verilog, created a structured test bench with predefined cases, and analyzed the simulation results. This assignment explored advanced Verilog concepts and complex digital design validation.\n## Assignment 3\nI developed a vending machine controller using the Spartan-6 FPGA in Xilinx ISE. The assignment focused on synthesizable finite state machine (FSM) designs. I coded and simulated the FSM module in Verilog, validating the design on the FPGA.\n## Assignment 4\nThe final assignment involved designing and implementing a 4-bit biquadratic filter algorithm on an FPGA. I optimized the design for speed and analyzed resource utilization and timing. Concepts covered included RTL code development, floating-point to fixed-point conversion, and FPGA optimizations.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmelvinmo%2Fhdl_course_archive","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmelvinmo%2Fhdl_course_archive","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmelvinmo%2Fhdl_course_archive/lists"}