{"id":29928645,"url":"https://github.com/meshiest/omegga-logic","last_synced_at":"2025-08-02T14:10:04.010Z","repository":{"id":44432206,"uuid":"342920671","full_name":"Meshiest/omegga-logic","owner":"Meshiest","description":"Logic simulator for omegga","archived":false,"fork":false,"pushed_at":"2022-07-15T03:36:56.000Z","size":1176,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":2,"default_branch":"master","last_synced_at":"2024-03-19T17:32:45.622Z","etag":null,"topics":["logic-simulator","omegga","plugin"],"latest_commit_sha":null,"homepage":"","language":"TypeScript","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"isc","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Meshiest.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2021-02-27T17:49:40.000Z","updated_at":"2024-03-19T17:32:45.623Z","dependencies_parsed_at":"2022-09-04T00:02:19.801Z","dependency_job_id":null,"html_url":"https://github.com/Meshiest/omegga-logic","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/Meshiest/omegga-logic","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Meshiest%2Fomegga-logic","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Meshiest%2Fomegga-logic/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Meshiest%2Fomegga-logic/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Meshiest%2Fomegga-logic/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Meshiest","download_url":"https://codeload.github.com/Meshiest/omegga-logic/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Meshiest%2Fomegga-logic/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":268401594,"owners_count":24244464,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-08-02T02:00:12.353Z","response_time":74,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["logic-simulator","omegga","plugin"],"created_at":"2025-08-02T14:10:03.154Z","updated_at":"2025-08-02T14:10:03.986Z","avatar_url":"https://github.com/Meshiest.png","language":"TypeScript","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Logic\n\nA logic simulator for [omegga](https://github.com/brickadia-community/omegga).\n\n## Install\n\n- `omegga install gh:meshiest/logic`\n\n## Usage\n\n1. Load the `logic bricks v2.brs` file for logic gate prefabs.\n2. Read the simulator rules below.\n3. Build some gates and wires.\n4. Run the simulation\n\n## Simulator rules\n\n### Construction\n\n- Wires must be 2x micro cube (smallest available) pipes (2x2xN) and have plastic material\n- Wires can connect to any wire of the same color within 1 microbrick in any direction (even diagonal)\n- Black wires (#000000) can connect to any color wire.\n- Gates can be made of any color, material, or brick type.\n  - Add `logic:gate:GATE` to the console tag on a brick's interact component. (eg. `logic:gate:AND`)\n- Gate connectables\n  - Add `logic:io:NAME` to the console tag on a brick's interact component (eg. `logic:io:input`)\n  - Connectables must be on top of the gate (Z Positive). This is hard to tell with microbricks.\n  - Wires connect to connectables adjacently\n  - Connectables are ordered by content after the `NAME[:\u003crest\u003e]`. `logic:io:input:00`, `logic:io:input:01`. This is a **string compare** so `10` will come before `1` but not `01`.\n  - Adding an `!` to the beginning of the interact tag (`!logic:gate:and`, `!logic:io:input`) **inverts** the input (on non-simple gates) or all output on the gate.\n- All i/o to gates is adjacent (wires cannot communicate with gates diagonally)\n- Wires cannot connect to the top and bottom of gates\n\n### Simulation\n\n- All gates are evaluated in order with input gates and `buffer`s first.\n- Default power state is off, so if a gate is not powering a wire it will be off.\n- Gates with clocks clock on the rising edge (off-\u003eon)\n- Cycles must be broken with the `buffer` gate.\n\n## Gates\n\n### Simple Gates\n\n| gate     | indicators        | description                              |\n| -------- | ----------------- | ---------------------------------------- |\n| `and`    | `input`, `output` | output is on when all input wires are on |\n| `or`     | `input`, `output` | output is on when any input wires are on |\n| `xor`    | `input`, `output` | output is on when one input wire is on   |\n| `buffer` | `input`, `output` | delays input by 1 tick                   |\n\n### Inputs (Triggered by clicking on the gate)\n\n| gate     | description                        |\n| -------- | ---------------------------------- |\n| `button` | when interacted, powers for 1 tick |\n| `lever`  | when interacted, toggles power     |\n\n### Outputs (Render bricks)\n\n| gate       | connectables                | description                                                                                                                                                                      |\n| ---------- | --------------------------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |\n| `pixel`    | `output`                    | Renders a glowing brick above the tile when powered                                                                                                                              |\n| `rgbpixel` | `color`, (optional `write`) | Renders above the baseplate with a brick 1stud bigger in each direction. Color based on bit input of the `color`. Always ON if no `write`, on if tile is powered or inverted+off |\n\n| gate          | connectables                                                         | description                                                                                                                                                                                                                                                                                                                                    |\n| ------------- | -------------------------------------------------------------------- | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |\n| `sr_latch`    | `input`, `reset`, `output`                                           | standard SR latch                                                                                                                                                                                                                                                                                                                              |\n| `d_flipflop`  | `input`, `clock` OR `write`, `output`                                | standard D flip flop                                                                                                                                                                                                                                                                                                                           |\n| `jk_flipflop` | `input`, `clock`, `reset`, `output` (optional `clear`)               | standard JK flip flop (`input`=J, `reset`=K)                                                                                                                                                                                                                                                                                                   |\n| `adder`       | `input`, `output`                                                    | an adder, counts the number of on inputs and outputs encoded value                                                                                                                                                                                                                                                                             |\n| `mux`         | `input`, `address`, `output`                                         | a multiplexer. requires #`output` to be divisible by #`input`s, `address` is the address, output is the value of the addressed `input`                                                                                                                                                                                                         |\n| `decoder`     | `input`, `disable`, `output`                                         | a decoder. requires #`output` to be 2^(#`input`-1), `disable` turns off output `input`                                                                                                                                                                                                                                                         |\n| `mem`         | `input`, `address`, (`write` OR `clock`), `output`, (optional `clr`) | a memory cell. stores (1\u003c\u003c#`address`) #`input`-bit values, `address` is the address. writes only when `write` is on or `clock` is clocked, outputs the currently addressed cell. There must be an equal number of inputs and outputs. `clr` clears all data. Adding `:fast` at the end of `io:write` will make the memory read before writing. |\n| `rom`         | `address`, `config`, `output`, `data`                                | ROM. requires #`output` to be divisible by the data sent to config (`logic:io:config:8`, 8 being the word size. ) `address` is the address, can output multiple words in series                                                                                                                                                                |\n\n## Commands\n\n- `/go` - compile the simulation\n  - `/go c` - compile the simulation for only bricks in clipboard\n  - `/go r` - automatically run the next 10000 frames\n  - `/go rc` - clipboard + auto run next 10k\n  - `/go w` - run without rendering wires (outputs only)\n  - `/go l` - run with loose octree mode (faster on more bricks)\n- `/next` - render the next frame of the simulation\n  - `/next 500 100` - render the next 500 frames of the simulation at 10fps (100ms per frame)\n  - `/next 500 100 5` - render the next 500 frames of the simulation at 50fps (100ms per 5 frames)\n- `/clg` - clear wire signal bricks\n- `!press` - press buttons/levers\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmeshiest%2Fomegga-logic","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmeshiest%2Fomegga-logic","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmeshiest%2Fomegga-logic/lists"}