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Build system files (e.g., make,\nninja) are then generated which shuttle files between nodes before\nrunning them.\n\n\u003cimg width='350px' src='docs/_static/images/example-graph.jpg'\u003e\n\nKey features and design philosophies:\n\n- **Process and technology independence** -- Process technology\n  libraries and variables can be abstracted and separated from\n  physical design scripts. Specifically, a single node called the\n  ASIC design kit (ADK) captures this material in one place for\n  better maintainability and access control.\n\n- **Sandboxed and modular nodes** -- Traditional ASIC flows are\n  composed of many steps executing with fixed path dependencies. The\n  resulting flows have low reusability across designs and technology\n  nodes and can be confusing and monolithic. In contrast,\n  _modularity_ encourages reuse of the same scripts across many\n  projects, while _sandboxing_ makes each node self-contained and\n  also makes the role of each node easy to understand (i.e., take\n  these inputs and generate those outputs).\n\n- **Programmatically defined build-system generator**: A\n  Python-based scripting interface and a simple graph API allows\n  flexible connection and disconnection of edges, insertion and\n  removal of nodes, and parameter space expansions. A simple graph\n  can be specified for a quick synthesis and place-and-route spin,\n  or a more complex graph can be built for a more aggressive chip\n  tapeout (reusing many of the same nodes from before).\n\n- **Run-time assertions** -- Assertions can be built into each\n  modular node and checked at run-time. Preconditions and\n  postconditions are simply Python snippets that run before and\n  after a node to catch unexpected situations that arise at build\n  time. Assertions are collected and run with pytest. The mflowgen\n  graph-building DSL can also extend a node with _design-specific_\n  assertions by extending Python lists.\n\n- **A focus on hardware design-space exploration** -- Parameter\n  expansion can be applied to nodes to quickly spin out parallel\n  builds for design-space exploration at both smaller scales with a\n  single parameter (e.g., sweeping clock targets) as well as at\n  larger scales with multiple parameters (e.g., to characterize the\n  area-energy tradeoff space of a new architectural widget with\n  different knobs). Dependent files are shuttled to each sandbox\n  as needed.\n\n- **Complete freedom in defining what nodes do** -- Aside from\n  exposing precisely what the inputs and outputs are, no other\n  restrictions are placed on what nodes do. A node may conduct an\n  analysis pass and report a gate count. A node can also apply a\n  transform pass to a netlist before passing it to other tools. In\n  addition, a node can even instantiate a subgraph to implement a\n  hierarchical flow.\n\nmflowgen ships with a limited set of ASIC flow scripts for both\nopen-source and commercial tools including synthesis (e.g., Synopsys\nDC, yosys), place and route (e.g., Cadence Innovus Foundation Flow,\nRePlAce, graywolf, qrouter), and signoff (e.g., Synopsys PTPX,\nMentor Calibre). In addition, we include an open-source 45nm ASIC design\nkit (ADK) assembled from FreePDK45 version 1.4 and the NanGate Open\nCell Library.\n\nMore info can be found in the\n[documentation](https://mflowgen.readthedocs.io/en/latest).\n\n--------------------------------------------------------------------------\nLicense\n--------------------------------------------------------------------------\n\nmflowgen is offered under the terms of the Open Source Initiative BSD\n3-Clause License. More information about this license can be found\nhere:\n\n- http://choosealicense.com/licenses/bsd-3-clause\n- http://opensource.org/licenses/BSD-3-Clause\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmflowgen%2Fmflowgen","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmflowgen%2Fmflowgen","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmflowgen%2Fmflowgen/lists"}