{"id":25970625,"url":"https://github.com/michaelehab/aes-verilog","last_synced_at":"2026-02-08T13:06:10.273Z","repository":{"id":50086788,"uuid":"487368446","full_name":"michaelehab/AES-Verilog","owner":"michaelehab","description":"Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL","archived":false,"fork":false,"pushed_at":"2022-07-31T19:58:08.000Z","size":9149,"stargazers_count":90,"open_issues_count":1,"forks_count":21,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-03-04T23:18:22.907Z","etag":null,"topics":["aes","aes-128","aes-192","aes-256","aes-decryption","aes-encryption","cryptography","encryption","encryption-decryption","fpga","fpga-board","fpga-soc","learn","rtl","security","verilog","verilog-hdl","verilog-project"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/michaelehab.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2022-04-30T19:52:31.000Z","updated_at":"2025-02-23T16:24:44.000Z","dependencies_parsed_at":"2022-09-24T11:42:02.601Z","dependency_job_id":null,"html_url":"https://github.com/michaelehab/AES-Verilog","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/michaelehab/AES-Verilog","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/michaelehab%2FAES-Verilog","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/michaelehab%2FAES-Verilog/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/michaelehab%2FAES-Verilog/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/michaelehab%2FAES-Verilog/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/michaelehab","download_url":"https://codeload.github.com/michaelehab/AES-Verilog/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/michaelehab%2FAES-Verilog/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":268256822,"owners_count":24221052,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-08-01T02:00:08.611Z","response_time":67,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["aes","aes-128","aes-192","aes-256","aes-decryption","aes-encryption","cryptography","encryption","encryption-decryption","fpga","fpga-board","fpga-soc","learn","rtl","security","verilog","verilog-hdl","verilog-project"],"created_at":"2025-03-04T23:18:25.059Z","updated_at":"2026-02-08T13:06:08.392Z","avatar_url":"https://github.com/michaelehab.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Advanced encryption standard (AES128, AES192, AES256) in Verilog\n![aes from Kekayan, Medium](https://user-images.githubusercontent.com/29122581/169694136-ca48f098-d5f5-448f-8016-4cb9a9b0e300.png)\n\u003cdiv align=\"center\"\u003e\n  \n  ![GitHub stars](https://img.shields.io/github/stars/michaelehab/AES-Verilog?style=plastic)\n  ![GitHub forks](https://img.shields.io/github/forks/michaelehab/AES-Verilog?style=plastic)\n  ![GitHub repo size](https://img.shields.io/github/repo-size/michaelehab/AES-Verilog?style=plastic)\n  ![GitHub top language](https://img.shields.io/github/languages/top/michaelehab/AES-Verilog?style=plastic)\n  \n\u003c/div\u003e\n\n# Explanation:\nThe Advanced Encryption Standard (AES) specifies a FIPS-approved\ncryptographic algorithm that can be used to protect electronic data. The AES algorithm is a\nsymmetric block cipher that can encrypt (encipher) and decrypt (decipher) information.\nEncryption converts data to an unintelligible form called ciphertext; decrypting the ciphertext\nconverts the data back into its original form, called plaintext.\nThe AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits to encrypt\nand decrypt data in blocks of 128 bits\n\n# Links\n* [Wikipedia](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard)\n* [NIST](./NIST.FIPS.197.pdf)\n\n# Usage\n\n**🔐Encryption: (AES_Encrypt module)**\n```verilog\n...\nwire[127:0] in = 128'h_00112233445566778899aabbccddeeff; // Plain Text example\n\nwire[127:0] key128 = 128'h_000102030405060708090a0b0c0d0e0f; // 128bit key\nwire[191:0] key192 = 192'h_000102030405060708090a0b0c0d0e0f1011121314151617; // 192bit key\nwire[255:0] key256 = 256'h_000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f; // 256bit key\n\nwire[127:0] encrypted128; // This wire will contain the encrypted text using the 128bit key\nwire[127:0] encrypted192; // This wire will contain the encrypted text using the 192bit key\nwire[127:0] encrypted256; // This wire will contain the encrypted text using the 256bit key\n\n// The encryption module uses AES128 by default\nAES_Encrypt a(in,key128,encrypted128);\n// You can pass the key length, Nr and Nk as parameters to use AES192 and AES256\nAES_Encrypt #(192,12,6) b(in,key192,encrypted192);\nAES_Encrypt #(256,14,8) c(in,key256,encrypted256);\n...\n```\n\n**🔓Decryption: (AES_Decrypt module)**\n```verilog\n...\n// This wire contains the encrypted text using the 128bit key\nwire[127:0] encrypted128 = 128'h_69c4e0d86a7b0430d8cdb78070b4c55a;\n// This wire contains the encrypted text using the 192bit key\nwire[127:0] encrypted192 = 128'h_dda97ca4864cdfe06eaf70a0ec0d7191;\n// This wire contains the encrypted text using the 256bit key\nwire[127:0] encrypted256 = 128'h_8ea2b7ca516745bfeafc49904b496089;\n\nwire[127:0] key128 = 128'h_000102030405060708090a0b0c0d0e0f; // 128bit key\nwire[191:0] key192 = 192'h_000102030405060708090a0b0c0d0e0f1011121314151617; // 192bit key\nwire[255:0] key256 = 256'h_000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f; // 256bit key\n\nwire[127:0] decrypted128; // This wire will contain the decrypted text using the 128bit key\nwire[127:0] decrypted192; // This wire will contain the decrypted text using the 192bit key\nwire[127:0] decrypted256; // This wire will contain the decrypted text using the 256bit key\n\n// The decryption module uses AES128 by default\nAES_Decrypt a2(encrypted128,key128,decrypted128);\n// You can pass the key length, Nr and Nk as parameters to use AES192 and AES256\nAES_Decrypt #(192,12,6) b2(encrypted192,key192,decrypted192);\nAES_Decrypt #(256,14,8) c2(encrypted256,key256,decrypted256);\n...\n```\n\n**Testing: (AES wrapper module)**\n```verilog\n...\n// All these wires are connected to leds\nwire e128; // This led will be turned on when AES128 Encryption test succeeds\nwire d128; // This led will be turned on when AES128 Decryption test succeeds\nwire e192; // This led will be turned on when AES192 Encryption test succeeds\nwire d192; // This led will be turned on when AES192 Decryption test succeeds\nwire e256; // This led will be turned on when AES256 Encryption test succeeds\nwire d256; // This led will be turned on when AES256 Decryption test succeeds\nreg enable; // This switch enables the wrapper module\n\nAES a(enable, e128, d128, e192, d192, e256, d256);\n...\n```\n\n# 📷 Working Images\nTesting was done on DE1-SOC kit by implementing the wrapper module which generates the required inputs to the system and if tests passed it turns on the LEDs.\n## Enable turned off\n![disabled](https://user-images.githubusercontent.com/29122581/170337017-2246f4cf-f74e-4cbb-b4d8-f79b7436e2bd.jpg)\n## Enable turned on\n![enabled](https://user-images.githubusercontent.com/29122581/170337046-f8e7831a-081f-4685-b5aa-f520870f6d48.jpg)\n\n\u003cdiv align=\"center\"\u003e\n  \n  ![GitHub Repo Visitors](https://api.visitorbadge.io/api/VisitorHit?user=michaelehab\u0026repo=AES-Verilog\u0026countColor=%237B1E7A)\n  \n\u003c/div\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmichaelehab%2Faes-verilog","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmichaelehab%2Faes-verilog","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmichaelehab%2Faes-verilog/lists"}