{"id":28577646,"url":"https://github.com/mightlaus/cla-full-adder","last_synced_at":"2026-01-29T09:09:24.437Z","repository":{"id":212777324,"uuid":"732292688","full_name":"Mightlaus/CLA-full-adder","owner":"Mightlaus","description":"A high-performance and versatile carry-lookahead (CLA) full adder designed for rapid addition of arbitrary x^y bit inputs.","archived":false,"fork":false,"pushed_at":"2023-12-16T07:35:53.000Z","size":19,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2023-12-16T08:45:56.560Z","etag":null,"topics":["adder","digital-circuits","high-performance","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Mightlaus.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2023-12-16T07:25:09.000Z","updated_at":"2023-12-16T08:45:58.417Z","dependencies_parsed_at":"2023-12-16T08:45:58.207Z","dependency_job_id":"e1b856c2-bc29-466b-bc97-7d96aee700c9","html_url":"https://github.com/Mightlaus/CLA-full-adder","commit_stats":null,"previous_names":["mightlaus/cla-full-adder"],"tags_count":0,"template":null,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mightlaus%2FCLA-full-adder","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mightlaus%2FCLA-full-adder/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mightlaus%2FCLA-full-adder/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mightlaus%2FCLA-full-adder/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Mightlaus","download_url":"https://codeload.github.com/Mightlaus/CLA-full-adder/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mightlaus%2FCLA-full-adder/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":259177341,"owners_count":22817349,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["adder","digital-circuits","high-performance","verilog"],"created_at":"2025-06-11T00:38:47.668Z","updated_at":"2026-01-29T09:09:24.376Z","avatar_url":"https://github.com/Mightlaus.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# CLA-full-adder\nA high-performance and versatile carry-lookahead (CLA) full adder designed for rapid addition of arbitrary x^y bit inputs.\n\n## Module Hierarchy\nThe project follows a modular structure, as illustrated below:\n```\nHierarchy\n( 1) └── fadd_tb.v\n( 2)     └── fadd.v\n( 3)         ├── Sum.v\n( 4)         ├── CLA.v\n( 5)         │   ├── CLA*.v\n( 6)         │   ├── CarryGen.v\n( 7)         │   └── PGxGen.v\n( 8)         └── PGGen.v\n\n* denotes a recursive implementation\n```\n- **fadd_tb.v**: The testbench for the full adder module.\n- **fadd.v**: The full adder module that orchestrates the addition process.\n- **Sum.v**: Module responsible for calculating the sum of the inputs.\n- **CLA.v**: Core carry-lookahead module.\n- **PGxGen.v**: Module responsible for generating propagate (P) and generate (G) signals across recursive levels.\n- **PGGen.v**: Module for generating propagate (P) and generate (G) signals of inputs.\n- **CarryGen.v**: Module for generating carry bits based on propagate (P) and generate (G) signals.\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmightlaus%2Fcla-full-adder","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmightlaus%2Fcla-full-adder","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmightlaus%2Fcla-full-adder/lists"}