{"id":13408649,"url":"https://github.com/mikeroyal/Verilog-SystemVerilog-Guide","last_synced_at":"2025-03-14T13:31:47.841Z","repository":{"id":49275640,"uuid":"321790120","full_name":"mikeroyal/Verilog-SystemVerilog-Guide","owner":"mikeroyal","description":"Verilog/SystemVerilog Guide","archived":false,"fork":false,"pushed_at":"2024-01-04T22:17:43.000Z","size":20,"stargazers_count":48,"open_issues_count":0,"forks_count":6,"subscribers_count":4,"default_branch":"main","last_synced_at":"2024-05-23T07:20:43.693Z","etag":null,"topics":["awesome","awesome-list","awesome-readme","fpga","hardware","systemverilog","verilog"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mikeroyal.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2020-12-15T21:12:03.000Z","updated_at":"2024-05-07T05:44:32.000Z","dependencies_parsed_at":"2024-01-11T20:42:38.173Z","dependency_job_id":"0b9d8bfc-ebc6-4253-9b4c-64b07f76d16d","html_url":"https://github.com/mikeroyal/Verilog-SystemVerilog-Guide","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mikeroyal%2FVerilog-SystemVerilog-Guide","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mikeroyal%2FVerilog-SystemVerilog-Guide/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mikeroyal%2FVerilog-SystemVerilog-Guide/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mikeroyal%2FVerilog-SystemVerilog-Guide/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mikeroyal","download_url":"https://codeload.github.com/mikeroyal/Verilog-SystemVerilog-Guide/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243584377,"owners_count":20314748,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["awesome","awesome-list","awesome-readme","fpga","hardware","systemverilog","verilog"],"created_at":"2024-07-30T20:00:54.349Z","updated_at":"2025-03-14T13:31:47.815Z","avatar_url":"https://github.com/mikeroyal.png","language":"SystemVerilog","funding_links":[],"categories":["Tutorials and Courses 💬[Intro](./Tutorials%20and%20Courses/README.md)","Awesome List"],"sub_categories":["HDL"],"readme":"\u003ch1 align=\"center\"\u003e\n \u003cimg src=\"https://user-images.githubusercontent.com/45159366/102273517-4b785480-3ed7-11eb-910a-113821428f17.png\"\u003e\n  \u003cbr /\u003e\n  Verilog/SystemVerilog Guide\n\u003c/h1\u003e\n\n \u003ca href=\"https://github.com/mikeroyal?tab=followers\"\u003e\n         \u003cimg alt=\"followers\" title=\"Follow me for Updates\" src=\"https://custom-icon-badges.demolab.com/github/followers/mikeroyal?color=236ad3\u0026labelColor=1155ba\u0026style=for-the-badge\u0026logo=person-add\u0026label=Follow\u0026logoColor=white\"/\u003e\u003c/a\u003e \t\n\n![Maintenance](https://img.shields.io/maintenance/yes/2024?style=for-the-badge)\n![Last-Commit](https://img.shields.io/github/last-commit/mikeroyal/verilog-systemverilog-guide?style=for-the-badge)\n         \n#### A guide covering Verilog \u0026 SystemVerilog including the applications, libraries and tools that will make you a better and more efficient developer by having a better understanding of how hardware works on the lowest level.\n\n**Note: You can easily convert this markdown file to a PDF in [VSCode](https://code.visualstudio.com/) using this handy extension [Markdown PDF](https://marketplace.visualstudio.com/items?itemName=yzane.markdown-pdf).**\n \n \u003cp align=\"center\"\u003e\n \u003cimg src=\"https://user-images.githubusercontent.com/45159366/122687554-e544f500-d1cb-11eb-90ed-a7accf7cf126.png\"\u003e\n  \u003cbr /\u003e\n\u003c/p\u003e\n\n#  Verilog/SystemVerilog Learning Resources\n\n[Verilog](https://verilog.com/) is a Hardware Description Language(HDL) used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction.\n\n[SystemVerilog](https://www.systemverilog.io/) is an extension of Verilog with many of the verification features that allow engineers to verify the design using complex testbench structures and random stimuli in simulation. \n\n[Verilog Book Shelf](https://verilog.com/v-books.html)\n\n[Verilog HDL Basics training from Intel](https://www.intel.com/content/www/us/en/programmable/support/training/course/ohdl1120.html)\n\n[SystemVerilog for Design and Verification](https://www.cadence.com/en_US/home/training/all-courses/82143.html)\n\n[Verilog HDL Programming Courses on Udemy](https://www.udemy.com/topic/verilog-hdl-programming/)\n\n[Top Verilog Programming Courses on Coursera](https://www.coursera.org/courses?query=verilog)\n\n[Verilog course for Engineers on Technobyte](https://technobyte.org/verilog-course-tutorials/)\n\n[Verilog Tutorials and Courses on hackr.io](https://hackr.io/tutorials/learn-verilog)\n\n[Designing With Verilog Certification from the Xilinx Learning Center](https://xilinxprod-catalog.netexam.com/Certification/35916/designing-with-verilog)\n\n[Learning Verilog for FPGA Development on LinkedIn Learning](https://www.linkedin.com/learning/learning-verilog-for-fpga-development)\n\n[SystemVerilog tutorial on ChipVerify](https://www.chipverify.com/systemverilog/systemverilog-tutorial)\n\n#  Verilog/SystemVerilog Tools \u0026 Frameworks\n\n[Apio](https://github.com/FPGAwars/apio) is a multiplatform toolbox, with static pre-built packages, project configuration tools and easy command interface to verify, synthesize, simulate and upload your verilog designs.\n\n[IceStorm](https://github.com/YosysHQ/icestorm) is a project that aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.\n\n[Icestudio](https://icestudio.io/) is a visual editor for open FPGA boards. Built on top of the Icestorm project using Apio.\n\n[EDA Playground](https://www.edaplayground.com) is a online code for programming your Verilog projects.\n\n[PlatformIO](https://platformio.org/) is a professional collaborative platform for embedded development with no vendor lock-in. It provides support for multiplatforms and frameworks such as IoT, Arduino, CMSIS, ESP-IDF, FreeRTOS, libOpenCM3, mbed OS, Pulp OS, SPL, STM32Cube, Zephyr RTOS, ARM, AVR, Espressif (ESP8266/ESP32), FPGA, MCS-51 (8051), MSP430, Nordic (nRF51/nRF52), NXP i.MX RT, PIC32, RISC-V.\n\n[PlatformIO for VSCode](https://marketplace.visualstudio.com/items?itemName=platformio.platformio-ide) is a plugin that provides support for the PlatformIO IDE on VSCode.\n\n[LLVM](https://llvm.org/) is a collection of modular and reusable compiler and toolchain technologies. It can be used to develop a front end for any programming language and a back end for any instruction set architecture(ISA). LLVM code representation is designed to be used in three different forms: as an in-memory compiler IR, as an on-disk bitcode representation (suitable for fast loading by a Just-In-Time compiler), and as a human readable assembly language representation.\n\n[Chisel](https://www.chisel-lang.org/) is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the [Scala](https://www.scala-lang.org/) programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.\n\n[Clash compiler](https://www.clash-lang.org/) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.\n\n[Verilator](https://verilator.org/) is an open-source SystemVerilog simulator and lint system.\n\n[Verilog to Routing(VTR)](https://verilogtorouting.org/) is a collaborative project to provide a open-source framework for conducting FPGA architecture and CAD Research \u0026 Development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.\n\n[Cascade](https://github.com/vmware/cascade) is a Just-In-Time Compiler for Verilog from VMware Research. Cascade executes code immediately in a software simulator, and performs compilation in the background. When compilation is finished, the code is moved into hardware, and from the user’s perspective it simply gets faster over time.\n\n[OpenTimer](https://github.com/OpenTimer/OpenTimer) is a High-Performance Timing Analysis Tool for VLSI Systems.\n\n\n## Contribute\n\n- [x] If would you like to contribute to this guide simply make a [Pull Request](https://github.com/mikeroyal/Verilog-SystemVerilog-Guide/pulls).\n\n\n## License\n\nDistributed under the [Creative Commons Attribution 4.0 International (CC BY 4.0) Public License](https://creativecommons.org/licenses/by/4.0/).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmikeroyal%2FVerilog-SystemVerilog-Guide","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmikeroyal%2FVerilog-SystemVerilog-Guide","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmikeroyal%2FVerilog-SystemVerilog-Guide/lists"}