{"id":15728183,"url":"https://github.com/mikeroyal/fpga-guide","last_synced_at":"2026-01-11T02:37:25.285Z","repository":{"id":103565106,"uuid":"328019296","full_name":"mikeroyal/FPGA-Guide","owner":"mikeroyal","description":"FPGA Guide","archived":false,"fork":false,"pushed_at":"2022-01-02T23:04:16.000Z","size":26,"stargazers_count":12,"open_issues_count":0,"forks_count":1,"subscribers_count":4,"default_branch":"main","last_synced_at":"2025-02-06T07:14:01.730Z","etag":null,"topics":["fpga","fpga-board","fpga-programming","fpga-soc","hardware","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mikeroyal.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-01-08T21:46:11.000Z","updated_at":"2025-01-18T12:37:25.000Z","dependencies_parsed_at":null,"dependency_job_id":"0b6f1ae5-fa8c-4388-856a-fff96f79a1b0","html_url":"https://github.com/mikeroyal/FPGA-Guide","commit_stats":{"total_commits":10,"total_committers":1,"mean_commits":10.0,"dds":0.0,"last_synced_commit":"e7e3e1012ee54ef14c2c196a9572f95ef1590695"},"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mikeroyal%2FFPGA-Guide","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mikeroyal%2FFPGA-Guide/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mikeroyal%2FFPGA-Guide/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mikeroyal%2FFPGA-Guide/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mikeroyal","download_url":"https://codeload.github.com/mikeroyal/FPGA-Guide/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246403902,"owners_count":20771527,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","fpga-board","fpga-programming","fpga-soc","hardware","verilog"],"created_at":"2024-10-03T23:01:20.145Z","updated_at":"2026-01-11T02:37:25.251Z","avatar_url":"https://github.com/mikeroyal.png","language":"Verilog","readme":"\u003ch1 align=\"center\"\u003e\n \u003cimg src=\"https://user-images.githubusercontent.com/45159366/104069966-ab060f00-51ba-11eb-8295-d3479b485c86.png\"\u003e\n  \u003cbr /\u003e\n  FPGA Guide\n\u003c/h1\u003e\n\n#### A guide covering FPGA(Field Programmable Gate Arrays) devices such as the PolarFire®, Artix 7 , Spartan 6  and Zynq-7000. Along with the tools, applications and libraries that will make you a better and more efficient developer with FPGA devices. Also, learn about cool projects that you can build with your FPGA device.\n\n**Note: You can easily convert this markdown file to a PDF in [VSCode](https://code.visualstudio.com/) using this handy extension [Markdown PDF](https://marketplace.visualstudio.com/items?itemName=yzane.markdown-pdf).**\n\n# Table of Contents\n\n1. [FPGA Development Boards](https://github.com/mikeroyal/FPGA-Guide#fpga-development-boards)\n\n2. [FPGA Learning Resources](https://github.com/mikeroyal/FPGA-Guide#fpga-learning-resources)\n\n3. [FPGA Tools](https://github.com/mikeroyal/FPGA-Guide#fpga-tools)\n \n \u003cp align=\"center\"\u003e\n \u003cimg src=\"https://user-images.githubusercontent.com/45159366/117887251-42f92f80-b265-11eb-868f-013a6fa7422f.png\"\u003e\n  \u003cbr /\u003e\n\u003c/p\u003e\n\nTesting a LabVIEW FPGA Design. Source: [NI](https://www.ni.com/en-us/shop/electronic-test-instrumentation/add-ons-for-electronic-test-and-instrumentation/what-is-labview-fpga-module.html)\n\n# FPGA Development Boards\n[Back to the Top](https://github.com/mikeroyal/FPGA-Guide#table-of-contents)\n\n[Checkout the PolarFire® FPGA Development Kits](https://www.microsemi.com/product-directory/dev-kits-solutions/3864-polarfire-kits)\n\n\u003cimg src=\"https://user-images.githubusercontent.com/45159366/104068349-97a67400-51b9-11eb-82b5-d06f804400ee.png\"\u003e\n\n\n[Checkout the Artix 7 FPGA Development board](https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/)\n\n\u003cimg src=\"https://user-images.githubusercontent.com/45159366/104068359-9d03be80-51b9-11eb-9bd2-0045e8f45eb9.png\"\u003e\n\n\n[Checkout the Spartan 6 FPGA Development board](https://store.digilentinc.com/anvyl-spartan-6-fpga-trainer-board/)\n\n\u003cimg src=\"https://user-images.githubusercontent.com/45159366/104068361-9e34eb80-51b9-11eb-9c68-0b59c5a107e1.png\"\u003e\n\n\n\n[Checkout the Zynq-7000 for ARM/FPGA SoC Development board](https://store.digilentinc.com/cora-z7-zynq-7000-single-core-and-dual-core-options-for-arm-fpga-soc-development/)\n\n\u003cimg src=\"https://user-images.githubusercontent.com/45159366/104068367-a12fdc00-51b9-11eb-966a-08a0868fcfb7.png\"\u003e\n\n\n## FPGA Learning Resources\n[Back to the Top](https://github.com/mikeroyal/FPGA-Guide#table-of-contents)\n \n[FPGA(Field Programmable Gate Arrays)](https://www.xilinx.com/products/silicon-devices/fpga/what-is-an-fpga.html) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing.\n\n[TinyFPGA](https://tinyfpga.com) is a new series of boards that are low-cost, [open source FPGA boards](https://github.com/tinyfpga) in a tiny form factor.\n\n[SiFive FPGA shells](https://github.com/sifive/fpga-shells)\n\n[FPGA \u0026 SoC Design Tools from Microsemi](https://www.microsemi.com/product-directory/fpga-soc/1637-design-resources)\n\n[QuickLogic Embedded FPGA (eFPGA) Intellectual Property (IP) and Software](https://www.quicklogic.com/products/efpga/efpga-ip-software/)\n\n[FPGA for Beginners with Development Boards from Digilent®](https://store.digilentinc.com/fpga-for-beginners/)\n\n[Hundreds of FPGA Projects on Instructables](https://www.instructables.com/circuits/howto/FPGA/)\n \n[FPGA Fundamentals from NI(National Instruments)](https://www.ni.com/en-us/innovations/white-papers/08/fpga-fundamentals.html)\n\n[Getting Started With LabVIEW FPGA from NI(National Instruments)](https://www.ni.com/tutorial/14532/en/)\n \n[Programming and FPGA Basics - INTEL® FPGAS](https://www.intel.com/content/www/us/en/products/programmable/fpga/new-to-fpgas/resource-center/overview.html)\n \n[Intel FPGA Training Program](https://www.intel.com/content/www/us/en/programmable/support/training/overview.html)\n \n[FPGA Courses on Coursera](https://www.coursera.org/courses?query=fpga)\n \n[FPGA Courses on Udemy](https://www.udemy.com/topic/fpga/)\n \n[FPGA Online Training Courses on LinkedIn Learning](https://www.linkedin.com/learning/topics/fpga)\n\n[UMass Lowell's Graduate Certificate in Field Programmable Gate Arrays(FPGA)](https://gps.uml.edu/certificates/grad/online-field-programmable-gate-arrays-bae-graduate-certificate.cfm)\n\n[FPGA Design Fundamentals Course (UC San Diego Extension)](https://extension.ucsd.edu/courses-and-programs/fpga-design-fundamentals)\n\n[FPGA II Course (UC San Diego Extension)](https://extension.ucsd.edu/courses-and-programs/fpga-embedded-design)\n\n[FPGAs \u0026 SoCs Training from Microsemi](https://www.microsemi.com/product-directory/training/4244-fpgas-socs-training)\n \n[DSP fundamentals for FPGAs course from MATLAB and Simulink Training](https://www.mathworks.com/training-schedule/dsp-for-fpgas.html)\n \n[Verilog Courses on Coursera](https://www.coursera.org/courses?query=verilog)\n\n\n## FPGA Tools\n[Back to the Top](https://github.com/mikeroyal/FPGA-Guide#table-of-contents)\n\n[LabVIEW FPGA](https://www.ni.com/en-us/shop/software/products/labview-fpga-module.html) is a software add-on for LabVIEW that you can use to more efficiently and effectively design FPGA-based systems through a highly integrated development environment, IP libraries, a high-fidelity simulator, and debugging features.\n\n[Apio](https://github.com/FPGAwars/apio) is a multiplatform toolbox, with static pre-built packages, project configuration tools and easy command interface to verify, synthesize, simulate and upload your verilog designs.\n\n[IceStorm](https://github.com/YosysHQ/icestorm) is a project that aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.\n\n[Icestudio](https://icestudio.io/) is a visual editor for open FPGA boards. Built on top of the Icestorm project using Apio.\n\n[FuseSoC](https://github.com/olofk/fusesoc) is an award-winning package manager and a set of build tools for HDL (Hardware Description Language) code and FPGA/ASIC development.\n \n[OpenWiFi](https://github.com/open-sdr/openwifi) is an open-source IEEE802.11/Wi-Fi baseband chip/FPGA design.\n \n[PipeCNN](https://github.com/doonny/PipeCNN) is an OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks (CNNs). Currently, there is a growing trend among developers in the FPGA community to utilize High Level Synthesis (HLS) tools to design and implement customized circuits on FPGAs.\n\n[Verilator](https://verilator.org/) is an open-source SystemVerilog simulator and lint system.\n\n[Verilog to Routing(VTR)](https://verilogtorouting.org/) is a collaborative project to provide a open-source framework for conducting FPGA architecture and CAD Research \u0026 Development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.\n\n[PlatformIO](https://platformio.org/) is a professional collaborative platform for embedded development with no vendor lock-in. It provides support for multiplatforms and frameworks such as IoT, Arduino, CMSIS, ESP-IDF, FreeRTOS, libOpenCM3, mbed OS, Pulp OS, SPL, STM32Cube, Zephyr RTOS, ARM, AVR, Espressif (ESP8266/ESP32), FPGA, MCS-51 (8051), MSP430, Nordic (nRF51/nRF52), NXP i.MX RT, PIC32, RISC-V.\n\n[PlatformIO for VSCode](https://marketplace.visualstudio.com/items?itemName=platformio.platformio-ide) is a plugin that provides support for the PlatformIO IDE on VSCode.\n \n[Tock](https://www.tockos.org/) is an embedded operating system designed for running multiple concurrent, mutually distrustful applications on Cortex-M and RISC-V based embedded platforms. Tock's design centers around protection, both from potentially malicious applications and from device drivers. \n\n[OpenTimer](https://github.com/OpenTimer/OpenTimer) is a High-Performance Timing Analysis Tool for VLSI Systems.\n\n[LLVM](https://github.com/llvm/) is a library that has collection of modular/reusable compiler and toolchain  components (assemblers, compilers, debuggers, etc.). With these components LLVM can be used as a compiler framework, providing a front-end(parser and lexer) and a back-end (code that converts LLVM's representation to actual machine code).\n\n[TinyGo](https://tinygo.org/) is a Go compiler(based on LLVM) intended for use in small places such as microcontrollers, WebAssembly (Wasm), and command-line tools.\n\n[Chipyard](https://chipyard.readthedocs.io/en/latest/) is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley](https://berkeley.edu/) projects to produce a RISC-V SoC with everything from MMIO-mapped peripherals to custom accelerators.\n\n[The Eclipse Embedded CDT](https://github.com/eclipse-embed-cdt/eclipse-plugins) is a collection of plug-ins for Arm \u0026 RISC-V C/C++ developers.\n[Unicorn](https://github.com/unicorn-engine/unicorn) is a lightweight, multi-platform, multi-architecture CPU emulator framework(ARM, AArch64, M68K, Mips, Sparc, X86) based on [QEMU](https://www.qemu.org/).\n\n[Keystone](https://github.com/keystone-engine/keystone) is a lightweight multi-platform, multi-architecture(Arm, Arm64, Hexagon, Mips, PowerPC, Sparc, SystemZ \u0026 X86) assembler framework.\n\n[Reko](https://github.com/uxmal/reko) is a decompiler for machine code binaries.\n\n[Renode](https://renode.io/) is [Antmicro's](https://antmicro.com) virtual development framework for multinode embedded networks (both wired and wireless) and is intended to enable a scalable workflow for creating effective, tested and secure IoT systems.\n\n[Diosix](https://diosix.org/) is a lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V.\n\n## Contribute\n\n- [x] If would you like to contribute to this guide simply make a [Pull Request](https://github.com/mikeroyal/FPGA-Guide/pulls).\n\n\n## License\n\n[Back to the Top](https://github.com/mikeroyal/FPGA-Guide#table-of-contents)\n\nDistributed under the [Creative Commons Attribution 4.0 International (CC BY 4.0) Public License](https://creativecommons.org/licenses/by/4.0/).\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmikeroyal%2Ffpga-guide","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmikeroyal%2Ffpga-guide","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmikeroyal%2Ffpga-guide/lists"}