{"id":36985596,"url":"https://github.com/mistert14-caen/logiccompiler","last_synced_at":"2026-01-13T23:02:42.245Z","repository":{"id":329156844,"uuid":"1118375841","full_name":"mistert14-caen/LogicCompiler","owner":"mistert14-caen","description":"Simulateur logique LogiSim équivalent pour le Web à des fins pédagogiques","archived":false,"fork":false,"pushed_at":"2025-12-29T13:17:49.000Z","size":394,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2026-01-13T19:46:28.853Z","etag":null,"topics":["equations","logic","parser","simulator"],"latest_commit_sha":null,"homepage":"https://mistert.freeboxos.fr/LogicCompiler2/?id=bcd_test","language":"JavaScript","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mistert14-caen.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2025-12-17T16:55:32.000Z","updated_at":"2025-12-29T13:17:53.000Z","dependencies_parsed_at":null,"dependency_job_id":null,"html_url":"https://github.com/mistert14-caen/LogicCompiler","commit_stats":null,"previous_names":["mistert14-caen/logiccompiler"],"tags_count":1,"template":false,"template_full_name":null,"purl":"pkg:github/mistert14-caen/LogicCompiler","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mistert14-caen%2FLogicCompiler","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mistert14-caen%2FLogicCompiler/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mistert14-caen%2FLogicCompiler/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mistert14-caen%2FLogicCompiler/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mistert14-caen","download_url":"https://codeload.github.com/mistert14-caen/LogicCompiler/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mistert14-caen%2FLogicCompiler/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28405148,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-13T21:51:37.118Z","status":"ssl_error","status_checked_at":"2026-01-13T21:45:14.585Z","response_time":56,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["equations","logic","parser","simulator"],"created_at":"2026-01-13T23:02:41.693Z","updated_at":"2026-01-13T23:02:42.239Z","avatar_url":"https://github.com/mistert14-caen.png","language":"JavaScript","funding_links":[],"categories":[],"sub_categories":[],"readme":"# LogicCompiler\n\nLogic Circuit Simulator – Extended Version\nPrésentation\n\nCe projet est une reprise et extension du dépôt original de Drendog :\nhttps://github.com/drendog/Logic-Circuit-Simulator\n\nL’objectif est d’enrichir le simulateur initial en lui ajoutant des capacités de description logique avancée, de hiérarchisation et d’encapsulation, tout en conservant l’ergonomie du wiring et de l’interface graphique existante.\n\n# Nouveautés principales\n\n **1. Parseur logique étendu**\n\nCette version intègre un parseur d’équations logiques capable de manipuler :\n\n  * des valeurs binaires (logique booléenne classique),\n\n  * des valeurs décimales, permettant de travailler sur des bus et des signaux multi-bits.\n\nIl devient ainsi possible de modéliser aussi bien des circuits combinatoires simples que des blocs plus complexes manipulant des mots binaires.\n\n**2. Prototypes logiques encapsulés**\n\nL’ajout majeur de cette version est la possibilité de définir des prototypes de fonctions logiques dans des fichiers texte.\n\nChaque prototype :\n\n  * décrit ses entrées, sorties et équations internes,\n\n  * est automatiquement lié au système de wiring du simulateur,\n\n  * se comporte comme un bloc encapsulé (boîte noire ou grise selon le niveau de détail souhaité).\n\nCe mécanisme introduit une hiérarchie logique, absente de la version initiale.\n\n**3. Système de sauvegarde repensé**\n\nLe système de sauvegarde a été modifié afin de :\n\n  * prendre en compte les nouveaux blocs importés,\n\n  * restaurer correctement les connexions (wires),\n\n  * préserver la cohérence entre l’interface graphique et le moteur logique.\n\n# Objectifs du projet\n\nL’objectif de ce travail est d’étendre les capacités du simulateur de Drendog pour se rapprocher :\n\n* d’un simulateur de type Logisim,\n\n* voire d’une approche inspirée de Verilog, mais orientée pédagogie et visualisation.\n\nLa présence de blocs hiérarchiques et encapsulés rend envisageable la simulation de systèmes plus complexes, comme par exemple un microprocesseur pédagogique de type SAP-1.\n\n# État du projet\n\nCe projet est en évolution active.\nIl sert à la fois :\n\n  * d’outil d’exploration technique,\n\n  * de support pédagogique,\n\n  * et de base expérimentale pour des architectures logiques hiérarchiques.\n\n\n# Exemples\n\n  * https://mistert.freeboxos.fr/LogicCompiler2/?id=demo\n\n  * https://mistert.freeboxos.fr/LogicCompiler2/?id=base\n\n  * https://mistert.freeboxos.fr/LogicCompiler2/?id=sap1 \n\n(Mettre programme 0F 2E E0 F0 00 00 00 00 00 00 00 00 00 00 01 05)\n\n  * https://mistert.freeboxos.fr/LogicCompiler2/?id=sap3-mini\n\n# Crédits\n\nProjet original : Drendog\nhttps://github.com/drendog/Logic-Circuit-Simulator\n\nExtensions et développements : MisterT\n\n# Licence\n\nMIT License\n\nCopyright (c) 2025 MisterT\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n\n\nConforme à la licence du projet original de Drendog.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmistert14-caen%2Flogiccompiler","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmistert14-caen%2Flogiccompiler","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmistert14-caen%2Flogiccompiler/lists"}