{"id":16352791,"url":"https://github.com/mixelpixel/computer-architecture-two","last_synced_at":"2025-04-12T20:32:39.821Z","repository":{"id":106835104,"uuid":"105079580","full_name":"mixelpixel/Computer-Architecture-Two","owner":"mixelpixel","description":"Computer Architecture - Peripherals: Network, DMA, Storage, Graphcis","archived":false,"fork":false,"pushed_at":"2017-10-01T21:08:16.000Z","size":48,"stargazers_count":1,"open_issues_count":0,"forks_count":51,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-03-26T14:55:59.603Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"JavaScript","has_issues":false,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mixelpixel.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null}},"created_at":"2017-09-27T23:26:42.000Z","updated_at":"2020-10-30T22:11:40.000Z","dependencies_parsed_at":null,"dependency_job_id":"09cb0057-0fbf-4e48-b74a-f672b7e78dfa","html_url":"https://github.com/mixelpixel/Computer-Architecture-Two","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mixelpixel%2FComputer-Architecture-Two","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mixelpixel%2FComputer-Architecture-Two/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mixelpixel%2FComputer-Architecture-Two/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mixelpixel%2FComputer-Architecture-Two/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mixelpixel","download_url":"https://codeload.github.com/mixelpixel/Computer-Architecture-Two/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248630242,"owners_count":21136404,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-10-11T01:27:30.894Z","updated_at":"2025-04-12T20:32:39.528Z","avatar_url":"https://github.com/mixelpixel.png","language":"JavaScript","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Peripherals\n\nPeripherals live on the front side bus with other fundamental components. Plugging a peripheral in via PCIx, SCSI, or SATA physically locates that device on the system bus. Other devices like USB devices exist on a separate bus from the system bus, but are synchronized with the system bus using a USB controller and a device driver that can translate USB bus messages into system bus messages.\n\n## Network interfaces\n\nIndependent processor caches network traffic:\n\n[OSI model](https://en.wikipedia.org/wiki/OSI_model)\n\nMemory address, stack pointer, data transmission rules\nProcessor communicates asynchronously over network connection in order to satisfy rules of protocol in use - either TCP or UDP.\n\nIP\n\n[Internet Protocol](https://en.wikipedia.org/wiki/Internet_Protocol)\n[Internet Protocol Suite](https://en.wikipedia.org/wiki/Internet_protocol_suite)\n\nTCP\n\n[Transmission Control Protocol](https://en.wikipedia.org/wiki/Transmission_Control_Protocol)\n\nUDP\n\n[User Datagram Protocol](https://en.wikipedia.org/wiki/User_Datagram_Protocol)\n\n#### More recommended reading\n\n[Just2Good Description of Networking](http://www.just2good.co.uk/networking.php)\n\n## DMA\n\n[Direct Memory Access](https://en.wikipedia.org/wiki/Direct_memory_access)\n\n### Hard disks\n\nPlatter-based hard disks used to be a very interesting subject of research and discussion. Imagine ultra-smooth platters spinning 100 times per second, with binary data encoded on them in sections \u003c 100 nanometers. The hard drive is the most space age piece of equipment in your home.\n\nYou can learn about them here:\n[Engineer Guy Hard Drive](https://en.wikipedia.org/wiki/File:Harddrive-engineerguy.ogv)\n\nPlatter based hard disks have an insane storage cost, less than $0.03 per gigabyte:\n\n[BackBlaze](https://www.backblaze.com/blog/hard-drive-cost-per-gigabyte/)\n\nSSDs are less interesting - they are just flash memory with a controller that engages your system's PCI bus.\n\n## Cyclic Redundancy Checking\n\n### Graphics Accelerators\n\nDedicated graphics pipelines - hardware designed just for manipulating pixels in an array and updating them in a shared memory used by the display. Separate pipeline from the CPU, again, graphics memory can be written to display without needing to be circled around with the CPU.\n\n#### Shaders\n\nC++ software (gsl, actually) that executes simple mathematics on every vertex simultaneously.\n\n#### Pipeline components\n\n#### Software components\n\nOpenGL, DirectX, WebGL. CUDA, GLSL\n\n#### Onboard memory\n\n# Assignment:\n\n1. The minimum seek time for an HDD is 9msec, and the maximum seek time is 90msec. The block size of this HDD is 4KB. How long on average does it take to read 100MB of data?\n\n2. Describe a TCP/IP packet in detail. Describe the header, how many bytes it is, and which components it contains. What data can come after the header?\n\n3. How does the network protocol guarantee that a TCP/IP packet is complete after transmission?\n\n4. What is the difference between TCP and IP?\n\n5. Why is 3d performance so much higher with a graphics card than without? Modern CPUs are extremely fast, what is limiting their performance?\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmixelpixel%2Fcomputer-architecture-two","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmixelpixel%2Fcomputer-architecture-two","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmixelpixel%2Fcomputer-architecture-two/lists"}