{"id":16653899,"url":"https://github.com/mixih/nail","last_synced_at":"2026-03-14T08:32:30.847Z","repository":{"id":213995752,"uuid":"735440061","full_name":"Mixih/NAIL","owner":"Mixih","description":"Common cross-design FPGA IP modules","archived":false,"fork":false,"pushed_at":"2024-01-09T06:38:33.000Z","size":62,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"mainline","last_synced_at":"2025-03-12T17:50:03.058Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"cern-ohl-s-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Mixih.png","metadata":{"files":{"readme":"README.adoc","changelog":null,"contributing":null,"funding":null,"license":"LICENSE_OHL-S-2.0","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2023-12-25T00:07:25.000Z","updated_at":"2024-01-09T06:28:54.000Z","dependencies_parsed_at":"2023-12-27T02:27:50.330Z","dependency_job_id":"58a03b18-888e-40ef-a3ce-515a0e87a3e1","html_url":"https://github.com/Mixih/NAIL","commit_stats":null,"previous_names":["mixih/iplib","mixih/nail"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/Mixih/NAIL","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mixih%2FNAIL","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mixih%2FNAIL/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mixih%2FNAIL/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mixih%2FNAIL/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Mixih","download_url":"https://codeload.github.com/Mixih/NAIL/tar.gz/refs/heads/mainline","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Mixih%2FNAIL/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28024530,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-12-25T02:00:05.988Z","response_time":58,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-10-12T09:47:58.890Z","updated_at":"2025-12-25T08:18:50.140Z","avatar_url":"https://github.com/Mixih.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"= Common FPGA IP Library\n\n== Description\n\nThis is a general collection of FPGA IP modules to make starting new designs easier. All\nmodules come with formal specification and/or behavioural validation testbenches to ensure\ncorrect functionality. Designs are generally optimized for the hardware primitives found\non modern Xilinx FPGAs (7 series and up), and use synthesis constructs that function well\nfor the Vivado synthesizer.\n\n== Interfaces and standards\n\nHere is a summary of the default interfaces that are used in the IP modules. Consult\nindividual IP documentation sheets for any deviations from these standards.\n\n[%autowidth]\n|===\n| Application | Interface | Notes\n\n| Streamed data           | AXI-S    | AXI-Stream, or extended AXI-Stream with backpressure feedback is acceptable.\n| Internal low-speed bus  | AXI-Lite | Wishbone may also be used.\n| Internal high-speed bus | TBD      | No IPs require a HS bus yet.\n| Audio                   | I2S      |\n|===\n\n== Requirements\n\n* Synthesis suite for hardware implementations (e.g. Xilinx VDS).\n* Verilator for simulation testbenches and linting.\n    ** Timing testbenches have been tested in Vivado xsim.\n    ** Icarus should also work in theory.\n* SymbiYosys (SBY) and baseline Yosys install for formal property verification and model\n  check.\n* CPP 20 compiler and CMake \u003e= 2.20 for the ipcore generators.\n\n== Usage\n\nDrop the entire `hdl/` folder into the design project and add all files to the design. A\ndependency resolution system and selective distribution builder will be created in the\nfuture to allow usage with hardware toolchains that require manual elaboration order\nspecification.\n\nFormal verification can be run by entering the `tb/formal` directory and \"making\" the\nproject using GNU make. It is heavily recommended to set the make `-j` jobs setting to the\nnumber of CPU cores to allow different IP modules to be verified in parallel.\n\n== Top-level directories\n\n* `doc`: Long-form test documentation.\n* `gen`: IP module configurators and generators if needed by given module.\n* `rtl`: Synthesizable RTL source files.\n* `tb`: Testbench and validation files.\n* `tools`: maintenance and utility tools for the repository.\n\n== Documentation\n\nSee the `doc/` folder.\n\n== FAQ\n\nQ: NAIL?\n\nA: \"commoN fpgA Ip Library\" (yes, this is a link:https://acronymify.com/[gratuitously constructed acronym])\n\nQ: So why does this exist? Don't most vendor toolchains come with large amounts of included IP.\n\nA: Good question! Firstly, writing blocks of reusable IP is quite educational. Secondly,\nvendor IP often is license encumbered, and somewhat difficult to integrate. Vendor IP also\nis usually encrypted, which makes debugging design issues very difficult, and greatly\nreduces the compatibility. Finally it is quite convenient to have a suite of IP with\ncopyright fully owned by a single entity for commercial purposes.\n\n\n== Licensing\n\n[IMPORTANT]\n====\nSynthesizable IP and testbench code in this repository is licensed under the CERN-OHL-S\nv2. This is the hardware equivalent to the GNU GPL license, with corresponding strongly\nreciprocal terms that bind derived and incorporating works under the same license.\n\nIf these license terms are unacceptable for any reason, a commercial-use, non-reciprocal\nlicense may be negotiated for each closed-source derivative project by contracting 0-PID\nTechnologies.\n====\n\nWe consider licensing to be an important part of establishing our rights to designs and\ndocumentation. To foster the open-hardware community while protecting our commercial\ninterests, we have elected to make IP available under the strongly reciprocal CERN OHL-S\nV2 license by default. This should be sufficient to enable other open hardware and\neducational projects to incorporate these IPs.\n\nNote that closed-source 3rd-party proprietary components, such as vendor provided\nencrypted IP, need only be made available in the format that is configurable and usable by\nthe synthesis tools per section 1.8 of CERN-OHL-S. (e.g. if you wish to incorporate Xilinx\nIP in any derived works, you must distribute the xci, coe, and bd files needed to\nconfigure and synthesize said IP). However unencrypted and first/second party IP used in\nderived works must be delivered in RTL form.\n\nPlease note that Verilator generated C++ sources produced from IP in this repository are\nstill bound by the original OHL-S-V2 license under the derived works clause.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmixih%2Fnail","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmixih%2Fnail","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmixih%2Fnail/lists"}