{"id":16239887,"url":"https://github.com/mr-sven/sim80c51","last_synced_at":"2025-04-08T09:26:40.968Z","repository":{"id":42391708,"uuid":"478932022","full_name":"mr-sven/Sim80C51","owner":"mr-sven","description":"80C51 Simulator and Listing Editor","archived":false,"fork":false,"pushed_at":"2024-12-11T14:05:51.000Z","size":387,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-02-14T06:27:43.061Z","etag":null,"topics":["8051","8051-microcontroller","8051-projects","80c51","80c552"],"latest_commit_sha":null,"homepage":"","language":"C#","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mr-sven.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-04-07T10:18:39.000Z","updated_at":"2024-12-11T14:05:55.000Z","dependencies_parsed_at":"2024-11-04T10:50:40.358Z","dependency_job_id":null,"html_url":"https://github.com/mr-sven/Sim80C51","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mr-sven%2FSim80C51","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mr-sven%2FSim80C51/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mr-sven%2FSim80C51/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mr-sven%2FSim80C51/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mr-sven","download_url":"https://codeload.github.com/mr-sven/Sim80C51/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247811490,"owners_count":21000113,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["8051","8051-microcontroller","8051-projects","80c51","80c552"],"created_at":"2024-10-10T13:45:30.179Z","updated_at":"2025-04-08T09:26:40.933Z","avatar_url":"https://github.com/mr-sven.png","language":"C#","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Sim80C51\n\nThis is an Application for generate listings from ROM dumps and simmulate 80C51 processor.\n\nCurrent implemented Processors:\n\n* Philips 80C552\n\nThe current workspace state, including memories and CPU state can be saved and loaded for continuing work or debugging later.\n\nYou can add multiple external RAM spaces direct empty or load a binary to a definded XRAM address.\n\nYou can also enable M48T Timekeeper function on every RAM block, it uses a `DispatcherTimer` to update the time in the M48T time registers. It supports stop functionalities via the control registers. Write is not supported it will always update the time from current system clock.\n\nEmpty RAMs are initialized with `0x00`, if using the M48T mode the second half of the RAM is initialized with `0xff` which is default by my analysis.\n\nAt the moment it is possible to Single Step the CPU and to Play/Pause the execution.\n\nNavigate from Breakpoint list to code and navigate to current `PC` is possible.\n\n![Main Window](mainwindow.jpg)\n\n## Listing Editor\n\nThe editor can load listings and import ROM dumps from binary or Intel HEX files.\n\nThe editor supports the following key commands at the moment:\n\n* B - add breakpoint\n* C - generate code from `DB` statement, possible switch case jumps `JMP @A+DPTR`\n* J - follow jump label\n* L - generate or update label\n* K - update comment\n* S - create string\n* U - undefine listing entry\n* X - show XRefs\n\n## Listing Format\n\nThe listings are stored and loaded in the following format:\n\n* ROM Address - 4 hex chars\n* two spaces\n* Instruction code - pairs of 2 hex chars devided by space\n* min two spaces\n* optional Label ending with `:`\n* min two spaces\n* Instruction\n* min one space\n* Instruction Arguments devided by `,`\n* Optional comment beginnig with `;`\n\nExample:\n```\n0000  02 01 00                 RESET:               LJMP  INIT\n0003  FF FF FF FF FF FF FF FF                       DB    ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh ; ........\n000B  C0 D0                    T0:                  PUSH  PSW\n000D  C0 E0                                         PUSH  ACC\n000F  C0 F0                                         PUSH  B\n```\n\nEvery unidentified code, empty memory or other data is grouped in `DB` instructions by the length of 8 bytes.\n\n## RAM View\n\nThe Core memory is splitted in up to three parts, the first part is the lower 128 byte addressable RAM, the second (yellow) is the upper 128 byte SFR, possible third (blue) is the 128 byte indirect addressable RAM if available.\n\nThe RAMs are direct editable, and saveable. Editing the SFR space is not updating the Processor UI because of missing `PropertyChanged` event on register name, but the register is updated. So it is recommendet to update the SFRs via the Processor UI.\n\nRAM save is available via Right-Click on the View.\n\n## Processor view\n\nThe Processor view is customized for each processor and shows all SFR values.\n\n## Adding a new Processor type\n\nAs reference use class `Sim80C51.Processors.P80C552`.\n\n* Extend `Sim80C51.Processors.C80C51` and `Sim80C51.Processors.I80C51`.\n* Override `Reset` method for initialize additional registers.\n* Use `DisplayName` Attribute for Dropdown text.\n* Create a `UserControl` for Processor View\n\nGetter and setter methods and `Interrupt` method using reflection to determine the caller.\n\n### Define interrupt method\n\nThe name format `Interrupt_\u003cIV\u003e` is required for the `ListingFactory` to determine the IV name. Use `IVAttribute` to specify the parameters.\n\n```csharp\n[IV(0x002B, 2)] // Interrupt entry address: 0x002B, Priority: 2\npublic void Interrupt_S1() { Interrupt(); } // Name S1\n```\n\n### Define a 8-bit register\n\nAssign the `SFRAttribute` to set the SFR address.\n\n```csharp\n[SFR(0xC6)]\npublic byte ADCH { get =\u003e GetMemFromProp(); set { SetMemFromProp(value); } }\n```\n\n### Define a 16-bit register\n\nAssign the `SFR16Attribute` to set the 8-bit register names, high and low.\n\n```csharp\n[SFR16(nameof(CTH3), nameof(CTL3))]\npublic ushort CT3 { get =\u003e GetMem16FromProp(); set { SetMem16FromProp(value); } }\n```\n\n### Define a single bit\n\nAssign the `SFRBitAttribute` to set the 8-bit register name and the bit number. If the bit is direct addressable, set `Addressable` parameter. Default is `false`.\n\n```csharp\n[SFRBit(nameof(S1CON), 0, true)]\npublic bool CR0 { get =\u003e GetBitFromProp(); set { SetBitFromProp(value); } }\n```\n\nBit fields on Ports P0 to P4 should not set the `Addressable` parameter, because they will be automatically declared as Addressable in the `ListingFactory` via the names `P0.0` to `P4.7`.\n\n## Things to do\n\n- [ ] check the EA bit on IEN0 Register set to disable all Interrupts\n- [ ] adding HD44780 display control\n- [ ] display PWM out based on Crystal speed\n- [ ] show serial baud based on Crystal speed\n- [ ] many more\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmr-sven%2Fsim80c51","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmr-sven%2Fsim80c51","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmr-sven%2Fsim80c51/lists"}