{"id":19347532,"url":"https://github.com/mrlsd/fpga","last_synced_at":"2026-03-02T10:32:35.735Z","repository":{"id":50749267,"uuid":"110830828","full_name":"mrLSD/fpga","owner":"mrLSD","description":"Research \u0026 Development FPGA projects for different boards","archived":false,"fork":false,"pushed_at":"2023-10-01T19:07:47.000Z","size":430,"stargazers_count":7,"open_issues_count":0,"forks_count":0,"subscribers_count":3,"default_branch":"master","last_synced_at":"2025-02-24T09:45:48.573Z","etag":null,"topics":["altera-fpga","fpga","sipeed-tang-nano-9k","systemverilog","verilog"],"latest_commit_sha":null,"homepage":"","language":"GLSL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mrLSD.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2017-11-15T12:30:15.000Z","updated_at":"2024-12-17T12:09:21.000Z","dependencies_parsed_at":"2025-01-07T03:03:10.318Z","dependency_job_id":null,"html_url":"https://github.com/mrLSD/fpga","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"purl":"pkg:github/mrLSD/fpga","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mrLSD%2Ffpga","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mrLSD%2Ffpga/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mrLSD%2Ffpga/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mrLSD%2Ffpga/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mrLSD","download_url":"https://codeload.github.com/mrLSD/fpga/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mrLSD%2Ffpga/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29998513,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-02T09:59:02.300Z","status":"ssl_error","status_checked_at":"2026-03-02T09:59:02.001Z","response_time":60,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["altera-fpga","fpga","sipeed-tang-nano-9k","systemverilog","verilog"],"created_at":"2024-11-10T04:16:52.679Z","updated_at":"2026-03-02T10:32:35.699Z","avatar_url":"https://github.com/mrLSD.png","language":"GLSL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# FPGA Research \u0026 Development\n\n## Supported boards\n\n- Altera devboard Cyclone IV E - `EP4CE10E22C8`\n- Sipeed TangNano 9k\n\n## Sipeed TangNano 9k\n\n- Usefull getting started guides:\n    - Sipeed [website]()\n    - [Lushat Labs articles](https://learn.lushaylabs.com/getting-setup-with-the-tang-nano-9k/#creating-a-new-project)\n- github examples:\n    - https://github.com/lushaylabs/tangnano9k-series-examples\n    - https://github.com/sipeed/TangNano-9K-example\n- required: [OSS Cad Suite](https://github.com/YosysHQ/oss-cad-suite-build) or just install [Gowin EDA](https://www.gowinsemi.com/en/support/download_eda/).\n\n### Altera Devboard\n\n- Devboard: `Cyclone IV E EP4CE10E22C8`\n- Quartus CAD required\nFPGA project mostly base on Verilog or SystemVerilog. And implemented for Altera DevelopmentBoard with Quartus CAD.\n\n#### Altera based projects\n\n* **VGA** - output via VGA interfact to motinors. Can draw multy line text with specific fonts.\n* **led4_highreg** - 12 LED circle sequence\n* **timer** - onboard digital LED count down timer with ability set timer time. \nDigital LED and Keys used for I/O.\n\n### LICENSE MIT\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmrlsd%2Ffpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmrlsd%2Ffpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmrlsd%2Ffpga/lists"}