{"id":19347502,"url":"https://github.com/mrlsd/mips-one-stage-cpu","last_synced_at":"2026-03-19T09:24:49.011Z","repository":{"id":50749318,"uuid":"197263932","full_name":"mrLSD/mips-one-stage-cpu","owner":"mrLSD","description":"MIPS 32 one stage CPU with limited ISA","archived":false,"fork":false,"pushed_at":"2019-07-16T20:43:17.000Z","size":4,"stargazers_count":1,"open_issues_count":0,"forks_count":1,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-02-24T09:45:46.815Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/mrLSD.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2019-07-16T20:35:13.000Z","updated_at":"2022-08-01T08:40:28.000Z","dependencies_parsed_at":"2022-09-02T23:51:42.572Z","dependency_job_id":null,"html_url":"https://github.com/mrLSD/mips-one-stage-cpu","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/mrLSD/mips-one-stage-cpu","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mrLSD%2Fmips-one-stage-cpu","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mrLSD%2Fmips-one-stage-cpu/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mrLSD%2Fmips-one-stage-cpu/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mrLSD%2Fmips-one-stage-cpu/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/mrLSD","download_url":"https://codeload.github.com/mrLSD/mips-one-stage-cpu/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mrLSD%2Fmips-one-stage-cpu/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29993376,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-02T01:47:34.672Z","status":"online","status_checked_at":"2026-03-02T02:00:07.342Z","response_time":60,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-10T04:16:42.811Z","updated_at":"2026-03-02T05:32:20.483Z","avatar_url":"https://github.com/mrLSD.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# MIPS 32 limited ISA CPU\n\nMIPS 32 1-stage CPU with limited ISA. Learning path for limited MIPS architecture.\n\n*Current supported opcodes*:\n* LW\n\nLICENSE: MIT\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmrlsd%2Fmips-one-stage-cpu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmrlsd%2Fmips-one-stage-cpu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmrlsd%2Fmips-one-stage-cpu/lists"}