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calculator written in Verilog-HDL.\nIt supports req/ack handshake protocol.\nI've tested on MU500-RX and DE1-SoC fpga board.\n\n## Required Tools\n\n- [Icarus Verilog(\u003e=10.0)](http://iverilog.wikia.com/wiki/Installation_Guide)\n- [Altera Quartus Prime(\u003e=15.0)](https://www.altera.co.jp/downloads/download-center.html)\n\n## Timing chart\n\n![](docs/timing_chart.png)\n\n66th Fibonacci number is `27777890035288`.\n\n## Source Code Organization\n\nThe source code is organized as follows:\n\n```text\ndocs/       documentation\nfpga/       fpga related files\nrtl/        RTL files for Motion Estimation Processor\ntestbench/  test suites\n```\n\n## Port declaration\n| Port name | IO     | Description               |\n| :-------  | :----: | :-----------------------  |\n| rst\\_n    | input  | low active reset          |\n| clk       | input  | clock signal              |\n| req       | input  | request for handshake     |\n| n         | input  | N'th fibonacci number     |\n| ack       | output | acknowledge for handshake |\n| result    | output | fibonacci number          |\n\n## Parameters\n\n| Name   | Description                |\n| :----- | :------------------------  |\n| N\\_IN  | bit width of input number  |\n| N\\_OUT | bit width of output number |\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmshr-h%2Ffibonacci_verilog","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmshr-h%2Ffibonacci_verilog","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmshr-h%2Ffibonacci_verilog/lists"}