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ANTLR4-Verilog-Python\nGenerated files from ANTLR4 for Verilog parsing in Python\n\n[![Build Status](https://img.shields.io/circleci/build/github/mtdsousa/antlr4-verilog-python?label=Continuous%20integration)](https://app.circleci.com/pipelines/github/mtdsousa/antlr4-verilog-python)\n![PyPI version](https://img.shields.io/pypi/v/antlr4-verilog)\n\n## Tutorial\nInstall this Python package\n```\npython3 -m pip install antlr4_verilog\n``` \n\nUse your own listener to walk through the AST:\n```python\nfrom antlr4_verilog import InputStream, CommonTokenStream, ParseTreeWalker\nfrom antlr4_verilog.verilog import VerilogLexer, VerilogParser, VerilogParserListener\n\ndesign = '''\n    module ha(a, b, sum, c);\n        input a, b;\n        output sum, c;\n\n        assign sum = a ^ b;\n        assign c = a \u0026 b;\n    endmodule\n'''\n\nclass ModuleIdentifierListener(VerilogParserListener):\n    def exitModule_declaration(self, ctx):\n        self.identifier = ctx.module_identifier().getText()\n\nlexer = VerilogLexer(InputStream(design))\nstream = CommonTokenStream(lexer)\nparser = VerilogParser(stream)\n\ntree = parser.source_text()\nlistener = ModuleIdentifierListener()\nwalker = ParseTreeWalker()\nwalker.walk(listener, tree)\nprint(listener.identifier) # 'ha'\n```\n\u003e Take a look at other listener methods for [Verilog](src/antlr4_verilog/verilog/VerilogParserListener.py) and [SystemVerilog](src/antlr4_verilog/systemverilog/SystemVerilogParserListener.py)\n\n\u003e You may find more examples in the [test file](test/test.py)\n\n## How to generate those files\n\nSystem requirements (Ubuntu):\n```\nsudo apt-get install -y default-jre\nsudo apt-get install -y default-jdk\nsudo apt-get install -y curl\n```\n\n1. Get ANTLR4:\n```bash\ncurl https://www.antlr.org/download/antlr-4.10.1-complete.jar -o extra/antlr-4.10.1-complete.jar\n```\n\n2. Get ANTLR grammars:\n```\ngit clone https://github.com/antlr/grammars-v4.git extra/grammars-v4\n```\n\n3. Call ANTLR for Verilog grammar:\n```\njava -Xmx500M -cp \"extra/antlr-4.10.1-complete.jar:${CLASSPATH}\" org.antlr.v4.Tool -Dlanguage=Python3 -visitor `pwd`/extra/grammars-v4/verilog/verilog/VerilogLexer.g4 `pwd`/extra/grammars-v4/verilog/verilog/VerilogParser.g4 `pwd`/extra/grammars-v4/verilog/verilog/VerilogPreParser.g4 -o src/antlr4_verilog/verilog\n```\n\n3. Call ANTLR for SystemVerilog grammar:\n```\njava -Xmx500M -cp \"extra/antlr-4.10.1-complete.jar:${CLASSPATH}\" org.antlr.v4.Tool -Dlanguage=Python3 -visitor `pwd`/extra/grammars-v4/verilog/systemverilog/SystemVerilogLexer.g4 `pwd`/extra/grammars-v4/verilog/systemverilog/SystemVerilogParser.g4 `pwd`/extra/grammars-v4/verilog/systemverilog/SystemVerilogPreParser.g4 -o src/antlr4_verilog/systemverilog\n```\n\n## How to test the grammar\n\n1. Generate Java files:\n```\njava -Xmx500M -cp \"extra/antlr-4.10.1-complete.jar:${CLASSPATH}\" org.antlr.v4.Tool -Dlanguage=Java -visitor `pwd`/extra/grammars-v4/verilog/verilog/VerilogLexer.g4 `pwd`/extra/grammars-v4/verilog/verilog/VerilogParser.g4 `pwd`/extra/grammars-v4/verilog/verilog/VerilogPreParser.g4 -o test/testrig/verilog\n```\n```\njava -Xmx500M -cp \"extra/antlr-4.10.1-complete.jar:${CLASSPATH}\" org.antlr.v4.Tool -Dlanguage=Java -visitor `pwd`/extra/grammars-v4/verilog/systemverilog/SystemVerilogLexer.g4 `pwd`/extra/grammars-v4/verilog/systemverilog/SystemVerilogParser.g4 `pwd`/extra/grammars-v4/verilog/systemverilog/SystemVerilogPreParser.g4 -o test/testrig/systemverilog\n```\n\n2. Compile these recently generated files:\n```\njavac -cp \"extra/antlr-4.10.1-complete.jar:${CLASSPATH}\" test/testrig/verilog/*.java\n```\n```\njavac -cp \"extra/antlr-4.10.1-complete.jar:${CLASSPATH}\" test/testrig/systemverilog/*.java\n```\n\n3. Create JAR files:\n``` \njar cf test/testrig/verilog.jar -C test/testrig/verilog .\n```\n``` \njar cf test/testrig/systemverilog.jar -C test/testrig/systemverilog .\n```\n\n4. Finally, for `test.v` and `test.sv` files:\n```\njava -Xmx500M -cp \"extra/antlr-4.10.1-complete.jar:test/testrig/verilog.jar:${CLASSPATH}\" org.antlr.v4.gui.TestRig Verilog source_text test/testrig/test.v -tree\n```\n```\njava -Xmx500M -cp \"extra/antlr-4.10.1-complete.jar:test/testrig/systemverilog.jar:${CLASSPATH}\" org.antlr.v4.gui.TestRig SystemVerilog source_text test/testrig/test.sv -tree\n```\n\u003e You can use `-gui` to test it interactively\n\n## Acknowledgement\nWe would like to appreciate the work from the ANTLR team and the Verilog/SystemVerilog grammar written by [Mustafa Said Ağca](https://github.com/msagca).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmtdsousa%2Fantlr4-verilog-python","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmtdsousa%2Fantlr4-verilog-python","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmtdsousa%2Fantlr4-verilog-python/lists"}