{"id":15220441,"url":"https://github.com/muhammadtalhasami/rv32i_single_cycle_logisim","last_synced_at":"2026-02-18T19:31:57.981Z","repository":{"id":232880068,"uuid":"785350374","full_name":"muhammadtalhasami/rv32I_single_cycle_logisim","owner":"muhammadtalhasami","description":"An implementation of rv32i single cycle processor on logisim","archived":false,"fork":false,"pushed_at":"2024-04-12T12:05:03.000Z","size":153,"stargazers_count":2,"open_issues_count":0,"forks_count":1,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-03-31T11:45:20.416Z","etag":null,"topics":["assembly-language","hardware","hardware-designs","logisim","microprocessor","rsic-v","rtl","rv32i","rv32i-processor","single-cycle","single-cycle-processor"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/muhammadtalhasami.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-04-11T17:59:49.000Z","updated_at":"2024-06-10T18:00:41.000Z","dependencies_parsed_at":null,"dependency_job_id":"bf3c11d9-6c87-4a10-a9d3-019dec6c5a24","html_url":"https://github.com/muhammadtalhasami/rv32I_single_cycle_logisim","commit_stats":null,"previous_names":["muhammadtalhasami/rv32i_single_cycle_logisim"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/muhammadtalhasami/rv32I_single_cycle_logisim","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/muhammadtalhasami%2Frv32I_single_cycle_logisim","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/muhammadtalhasami%2Frv32I_single_cycle_logisim/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/muhammadtalhasami%2Frv32I_single_cycle_logisim/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/muhammadtalhasami%2Frv32I_single_cycle_logisim/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/muhammadtalhasami","download_url":"https://codeload.github.com/muhammadtalhasami/rv32I_single_cycle_logisim/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/muhammadtalhasami%2Frv32I_single_cycle_logisim/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":279001277,"owners_count":26083040,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-10-09T02:00:07.460Z","response_time":59,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["assembly-language","hardware","hardware-designs","logisim","microprocessor","rsic-v","rtl","rv32i","rv32i-processor","single-cycle","single-cycle-processor"],"created_at":"2024-09-28T13:09:35.842Z","updated_at":"2025-10-09T10:39:33.777Z","avatar_url":"https://github.com/muhammadtalhasami.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"## RV32I Single Cycle Processor Implementation on Logisim\n\n\n\u003cimg src=\"https://github.com/muhammadtalhasami/rv32I_single_cycle_logisim/blob/main/single%20cycle%20logisim.jpeg\"\u003e\n\nThis project implements a single-cycle processor based on the RV32I instruction set architecture using Logisim, a digital circuit simulation tool. The processor supports 32-bit RISC-V instructions and executes them in a single clock cycle.\nFeatures\n\n    RV32I Instruction Set: Full support for the RV32I instruction set architecture, including arithmetic, logical, control transfer, and memory access instructions.\n    Single Cycle Execution: Each instruction is executed in a single clock cycle, simplifying the design and providing deterministic performance.\n    Logisim Simulation: The processor design is simulated and tested using Logisim, allowing for easy visualization and verification of the circuit behavior.\n    Modular Design: The processor is designed with modularity in mind, facilitating easy expansion and modification for future enhancements or customizations.\n    Documentation: Comprehensive documentation is provided to explain the design choices, implementation details, and usage instructions.\n\n## source code\n\n### Test cases\n\n#### Program 1\n```\ntop:\naddi x2,x0,10\nadd  x2,x2,x2\njal x1,jump\naddi x3,x2,30\nlui x4,1\nauipc x5,0x1000\nbne x2,x3,label\njump:\nadd x6,x3,x2\njalr x0,x1,0x0\nlabel:\nsw x6,0x4(x2)\nlw x7,0x4(x2)\njal x1,top\n```\n#### Dump code 1\n```\n00A00113\n00210133\n014000EF\n01E10193\n00001237\n01000297\n00311663\n00218333\n00008067\n00612223\n00412383\nFD5FF0EF\n```\n\n#### Program 2\n```\naddi x5 x0 0\naddi x6 x0 5\nadd x8 x6 x5\nLOOP:\naddi x5 x5 1\nsw x5 100(x0)\nbeq x5 x6 ANS\njal LOOP\nANS: lw x7 100(x0)\n```\n\n#### Dump code 2\n```\n00000293\n00500313\n00530433\n00128293\n06502223\n00628463\nFF5FF0EF\n06402383\n```\n\n\n#### Program 3\n```\naddi x5 x0 3\nLOOP:\naddi x5 x5 1\naddi x6 x0 7\nsw x6 100(x5)\nlw x7 100(x5)\nbne x5 x7 LOOP\n```\n\n#### Dump code 3\n```\n00300293\n00128293\n00700313\n0662A223\n0642A383\nFE7298E3\n```\n\n#### Program 4\n```\naddi x5 x0 0\naddi x7 x0 1\naddi x6 x0 10\naddi x28 x0 0\nLOOP: beq x28 x6 END\nadd x29 x5 x7\nadd x5 x0 x7\nadd x7 x0 x29\njal LOOP\nEND:\n```\n\n\n#### Dump code 4\n```\n00000293\n00100393\n00A00313\n00000E13\n006E0A63\n00728EB3\n007002B3\n01D003B3\nFF1FF0EF\n```\n\n#### Fibonacci Series:\n```\naddi x1,x0,0\naddi x2,x0,1\naddi x10,x0,4\naddi x6,x0,40\naddi x3,x0,0\naddi x4,x3,4\nsw x1,0x100(x3)\nsw x2,0x100(x4)\naddi x14,x0,8\naddi x5,x0,8\naddi x13,x0,8\naddi x15,x0,4\naddi x9,x0,4\nadd x8,x1,x2\nup:\nbeq x5,x6,end\nadd x12,x0,x8\nsw x12,0x100(x5)\nlw x11,0x100(x9)\nadd x8,x11,x8\naddi x5,x5,4\naddi x9,x9,4\njal x7,up\nend:\nbeq x3,x6,break\nlw x16,0x100(x3)\naddi x3,x3,4\njal x7,end\nbreak:\n```\n\n#### Dump code \n```\n00000093\n00100113\n00400513\n02800313\n00000193\n00418213\n1011A023\n10222023\n00800713\n00800293\n00800693\n00400793\n00400493\n00208433\n02628063\n00800633\n10C2A023\n1004A583\n00858433\n00428293\n00448493\nFE5FF3EF\n00618863\n1001A803\n00418193\nFF5FF3EF\n```\n\n\n\n## Getting Started\n\nTo simulate the RV32I single-cycle processor on your local machine, follow these steps:\n\nClone the Repository: Clone this GitHub repository to your local machine using the following command:\n\n\n\n    git clone git@github.com:muhammadtalhasami/rv32I_single_cycle_logisim.git\n\n\n## Contributing\n\nContributions are welcome! If you find any issues or have suggestions for improvements, feel free to open an issue or submit a pull request. Please follow the contribution guidelines when contributing to this project.\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmuhammadtalhasami%2Frv32i_single_cycle_logisim","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fmuhammadtalhasami%2Frv32i_single_cycle_logisim","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fmuhammadtalhasami%2Frv32i_single_cycle_logisim/lists"}