{"id":21882371,"url":"https://github.com/namn-grg/instruction-set-simulator","last_synced_at":"2026-05-10T06:32:58.788Z","repository":{"id":55463209,"uuid":"523080738","full_name":"namn-grg/Instruction-Set-Simulator","owner":"namn-grg","description":"Mimics the behavior of a mainframe or microprocessor by \"reading\" instructions and maintaining internal variables which represent the processor's registers.","archived":false,"fork":false,"pushed_at":"2022-08-09T19:44:19.000Z","size":159,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-01-26T19:14:22.336Z","etag":null,"topics":["python3","simulator"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/namn-grg.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2022-08-09T19:20:12.000Z","updated_at":"2022-08-09T19:44:22.000Z","dependencies_parsed_at":"2022-08-15T01:00:13.220Z","dependency_job_id":null,"html_url":"https://github.com/namn-grg/Instruction-Set-Simulator","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/namn-grg%2FInstruction-Set-Simulator","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/namn-grg%2FInstruction-Set-Simulator/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/namn-grg%2FInstruction-Set-Simulator/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/namn-grg%2FInstruction-Set-Simulator/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/namn-grg","download_url":"https://codeload.github.com/namn-grg/Instruction-Set-Simulator/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":244890097,"owners_count":20527035,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["python3","simulator"],"created_at":"2024-11-28T09:28:39.886Z","updated_at":"2026-05-10T06:32:58.755Z","avatar_url":"https://github.com/namn-grg.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Instruction-Set-Simulator\nIt mimics the behavior of a mainframe or microprocessor by \"reading\" instructions and maintaining internal variables which represent the processor's registers\nand flags. This simulator has its own Instruction Set Architecture (ISA)  and it follow VON NEUMANN ARCHITECTURE \n**************************************************************************************************************************************************************\nA synopsis of the ISA is given below (please read the pdf for the complete discription of the ISA)\n\nThe ISA has 7 general purpose registers and 1 flag register. The ISA supports an address size\nof 8 bits, which is double byte addressable. Therefore, each address fetches two bytes of\ndata. This results in a total address space of 512 bytes. This ISA only supports whole\nnumber arithmetic and also some floating point number arithmetic. \nIf the subtraction results in a negative number; for example “3 - 4”, the reg\nvalue will be set to 0 and overflow bit will be set. All the representations of the number are\nhence unsigned.\nThe registers in assembly are named as R0, R1, R2, ... , R6 and FLAGS. Each register is 16\nbits.\nThe floating point representaion is No sign bit, 3 exponent bit, 5 mantissa bit.\nWhile doing floating point arithmetic in the registers, only the last 8 bits will be used in computations and initialization for the\nfloating-point numbers.\n\n**************************************************************************************************************************************************************\nThere is a sample test case input file, you can take a look how input file look like and there is the correspoindig output file for the same. \nThe output file keeps track of flags and values stored in registers after execution of every instruction. At the end of the execution there is a memory dump \nof 256 lines. Memory dump describes how variables and program are stored in the same memory.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnamn-grg%2Finstruction-set-simulator","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fnamn-grg%2Finstruction-set-simulator","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnamn-grg%2Finstruction-set-simulator/lists"}