{"id":26571832,"url":"https://github.com/nathsou/yodl","last_synced_at":"2026-01-05T01:37:21.645Z","repository":{"id":281063836,"uuid":"899241448","full_name":"nathsou/yodl","owner":"nathsou","description":"Yet anOther hardware Description Language","archived":false,"fork":false,"pushed_at":"2025-03-15T21:07:22.000Z","size":2449,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-03-15T22:19:27.148Z","etag":null,"topics":["chisel","circuit","firrtl","fpga","hardware-description-language","hdl","verilog"],"latest_commit_sha":null,"homepage":"https://nathsou.github.io/yodl/playground.html","language":"MoonBit","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/nathsou.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-12-05T21:56:50.000Z","updated_at":"2025-03-15T21:06:49.000Z","dependencies_parsed_at":"2025-03-06T20:22:27.814Z","dependency_job_id":"f9c51c98-af41-46b9-b6e1-a3b46c91d7ad","html_url":"https://github.com/nathsou/yodl","commit_stats":null,"previous_names":["nathsou/yodl"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nathsou%2Fyodl","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nathsou%2Fyodl/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nathsou%2Fyodl/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nathsou%2Fyodl/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/nathsou","download_url":"https://codeload.github.com/nathsou/yodl/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":245031513,"owners_count":20549926,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chisel","circuit","firrtl","fpga","hardware-description-language","hdl","verilog"],"created_at":"2025-03-22T23:16:42.103Z","updated_at":"2026-01-05T01:37:21.639Z","avatar_url":"https://github.com/nathsou.png","language":"MoonBit","funding_links":[],"categories":[],"sub_categories":[],"readme":"# yodl\n\nYet anOther (hardware) Description Language\n\n\u003cimg src=\"res/gol.png\" alt=\"Parallel Game Of Life\" width=\"480px\"/\u003e\n\n## Quick links\n\n- [Documentation](https://nathsou.github.io/yodl/book/)\n- [Playground](https://nathsou.github.io/yodl/playground.html)\n\n# Installation\n\nThe JS build of Yodl can be installed from npm:\n\n```bash\n$ npm install --global yodl\n```\n\nTo compile FIRRTL outputs to SystemVerilog, install [firtool](https://github.com/llvm/circt/releases/tag/firtool-1.129.0)\n\n## Usage\n```bash\n$ yodl examples/Hello.yodl \"write_firrtl Hello.fir\"\n$ firtool --format=fir --verilog Hello.fir -o Hello.sv\n```\n\n## Development\nInstall [Moonbit](https://www.moonbitlang.com/):\n\n```bash\n$ curl -fsSL https://cli.moonbitlang.com/install/unix.sh | bash -s '0.6.35+dd17327ed'\n```\n\n## Checklist\n\n- [x] [FIRRTL](https://github.com/chipsalliance/firrtl-spec) export\n- [x] Generic multi-port memories\n- [x] Imports (TODO: unqualified imports)\n- [x] Verilator + SDL graphics simulation example\n- [x] Multi-dimensional vectors (uint\u003c16\u003e[4][8])\n- [ ] Optional module parameters (and register initial value)\n- [x] Arbitrary port types\n- [x] Type parameters\n- [x] External modules\n- [ ] Source Maps\n- [ ] Test Benches\n- [X] FIRRTL to RTLIL backend to bypass SystemVerilog generation\n- [ ] Language Server Protocol (LSP) support\n- [ ] [KiCad schematics](https://dev-docs.kicad.org/en/file-formats/sexpr-schematic/index.html) export\n- [x] Web tour/playground\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnathsou%2Fyodl","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fnathsou%2Fyodl","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnathsou%2Fyodl/lists"}