{"id":19065393,"url":"https://github.com/newaetech/fpga-common","last_synced_at":"2026-02-26T21:01:29.377Z","repository":{"id":84256196,"uuid":"589731843","full_name":"newaetech/fpga-common","owner":"newaetech","description":"FPGA design elements used across multiple projects.","archived":false,"fork":false,"pushed_at":"2025-11-29T00:42:27.000Z","size":223,"stargazers_count":3,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2026-01-19T19:41:17.134Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/newaetech.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2023-01-16T20:02:44.000Z","updated_at":"2025-11-29T00:42:32.000Z","dependencies_parsed_at":"2023-12-15T19:58:14.539Z","dependency_job_id":"de11516e-7308-4c52-acae-9439e17d3ee2","html_url":"https://github.com/newaetech/fpga-common","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/newaetech/fpga-common","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/newaetech%2Ffpga-common","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/newaetech%2Ffpga-common/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/newaetech%2Ffpga-common/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/newaetech%2Ffpga-common/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/newaetech","download_url":"https://codeload.github.com/newaetech/fpga-common/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/newaetech%2Ffpga-common/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29872669,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-26T18:42:30.764Z","status":"ssl_error","status_checked_at":"2026-02-26T18:41:47.936Z","response_time":89,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-09T00:49:47.620Z","updated_at":"2026-02-26T21:01:29.350Z","avatar_url":"https://github.com/newaetech.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"This repository contains Verilog modules that are common to multiple NewAE\nprojects.\n\n# Notes regarding FIFOs\nThese FIFOs were developed to overcome issues with simulating the Xilinx FIFOs\nwith the Icarus Verilog simulator. They are not (yet) intended to be a full\nreplacement for Xilinx FIFOs in implementation. Tests show that the Xilinx\nFIFOs result in better resource utilization and timing closure. However,\nthese FIFOs simulate *much* faster than the Xilinx ones.\n\nThe [fifo\\_sync](hdl/fifo_sync.v) module aims to have the exact same\nbehaviour as the Xilinx synchronous FIFO, and while there is some limited\ntesting for this, this is not exhaustively tested or proven (yet).\n\nThe [fifo\\_async](hdl/fifo_async.v) currently does *not* have the same\nbehaviour as the Xilinx asynchronous FIFO (i.e. in terms of timing of its\nempty/full status signals).\n\n\n# Notes regarding SS2 wrapper\n[ss2.v](hdl/ss2.v) implements the [SimpleSerial\nv2.1](https://chipwhisperer.readthedocs.io/en/latest/simpleserial.html#simpleserial-v2-1)\nprotocol (SS2) and maps SS2 commands to CW305 register read/writes. This allows\nexisting CW305 design which use the SAM3U USB parallel interface to be\nvery easily ported to the CW312T-A35 and CW312T-iCE40 target boards. \n\nExamples exist\nfor our existing [CW305 AES](https://github.com/newaetech/chipwhisperer/blob/develop/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2_cw305_aes.xpr), \n[CW305 AES pipeline](https://github.com/newaetech/chipwhisperer/blob/develop/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2_cw305_aes_pipelined.xpr) \nand [CW305 ECC](https://github.com/newaetech/chipwhisperer/blob/develop/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2_cw305_ecc.xpr) projects, ported to the CW312T-A35.\n\nFor the iCE40, there is the [CW305\nAES](https://github.com/newaetech/chipwhisperer/tree/develop/hardware/victims/cw308_ufo_target/ice40up5k/ss2_aes_icestorm)\nproject.\n\n\n### SS2 Wrapper Usage\nThe SS2 wrapper was designed to minimize the work required to port CW305 target\ndesigns to target platforms which lack the CW305's SAM3U USB parallel\ninterface, on both the FPGA development side and the host Python side (for\nCW305 designs that follow our example AES/ECC designs). \n\nOn the Verilog side, refer to the AES and ECC examples linked above to see\nwhat's needed. As per these examples, the wrapped CW305 top level module's\n`pBYTECNT_SIZE` parameter should be set to 8, and its `pADDR_WIDTH`\nparameter should be set to 32. The latter is required by `ss2.v`; the former\ncould in theory be changed, but\n[CW305.py](../../../../software/chipwhisperer/capture/targets/CW305.py)\nexpects it to be 8. Stray from these recommended values at your own risk.\n\nOn the Python side, connect to an SS2 target design by adding the `platform`\nargument:\n\n`target = cw.target(scope, cw.targets.CW305, bsfile=\u003cbitstream file\u003e, platform='ss2')`\n\nand everything should \"just work\". Calls to methods tied to CW305-specific\nhardware which does not exist on the CW312T-A35 or CW312T-iCE40 (external PLL,\nprogrammable supply voltage, USB clocking) will result in warnings.\n\nLook at the CW305 \n[AES](https://github.com/newaetech/chipwhisperer-jupyter/blob/master/demos/PA_HW_CW305_1-Attacking_AES_on_an_FPGA.ipynb)\nand \n[ECC](https://github.com/newaetech/chipwhisperer-jupyter/blob/master/demos/CW305_ECC/CW305_ECC_part1.ipynb)\nnotebooks to see how the same Python code can interact with a CW305 target\nrunning on either the CW305 natively, or wrapped by SS2 on the CW312T-A35 /\nCW312T-iCE40.\n\n\n### SS2 Wrapper Resource Overhead\nThe SS2 wrapper uses relatively little FPGA resources: 2% of the xc7a35's slice\nLUTs and less than 1% of its slice registers.\n\nOn the much smaller iCE40, the overhead is much more significant: 20% of logic\ncells. However, the [basic CW305 AES\ntarget](https://github.com/newaetech/chipwhisperer/tree/develop/hardware/victims/cw308_ufo_target/ice40up5k/ss2_aes_icestorm)\ndoes fit (*just barely!*).\n\n\n### SS2 Wrapper Clocking\nThe SS2 wrapper easily meets timing at 100 MHz on Xilinx 7-series. However it\nis intended to be clocked at 7.37 MHz since its baud rate (230400 bps) is\nhard-coded in the Verilog source.  This can be easily modified via the\n`pBIT_RATE` parameter in ss2.v, which indicates the number of clock cycles per\nUART bit. Of course it's also possible to scale the clock rate and baud rate\ntogether (e.g.  double the baud rate to 230400 * 2 = 460800 bps and double the\nclock rate to 7.37e6 * 2 = 14.74e6 MHz).\n\n\n### SS2 Wrapper Performance\nWhile SimpleSerial v2.1 runs at a speedy 230400 baud, it is still\nconsiderably slower than the CW305's SAM3U-based parallel register\ninterface. You can expect captures to run at about half the rate they would\non the CW305. Performance will depend on the length of the target operation\nand the number and size of the target reads and writes that are required.\n\n\n### SS2 Wrapper Commands\nMost SS2 wrapper commands use 0x23 as a command byte. The SS2 wrapper\nsupports 3 subcommands:\n\n* write: `cmd=0x23, scmd=0x57, dlen=[size of data], data=[4-byte address, write data]`\n* read: `cmd=0x23, scmd=0x52, dlen=5, data=[4-byte address, number of bytes to read]`\n* echo: `cmd=0x23, scmd=0x45, dlen=4, data=[4-byte payload]`\n\nThe purpose of the echo command is to test that UART communication is up: it\nis handled automatically by the SS2 wrapper without involving the underlying\ntarget.\n\nThese commands are exhaustively tested in simulation by the [SS2 testbench](sim/test_ss2.py).\n\nThere is also a command to reset the SS2 wrapper (and only the SS2 wrapper):\n* ss2\\_reset: `cmd=0x24, scmd=0x72, dlen=1, data=[single byte (not used)]`\n\n(This is not yet properly validated in simulation, but on-target testing shows\nthat it works as intended.)\n\nIf you use\n[CW305.py](../../../../software/chipwhisperer/capture/targets/CW305.py) then\nyou don't need to know about these details; everything is handled\nunder-the-hood by mapping `fpga_write()` and `fpga_read()` to the\ncorresponding SS2 commands.\n\n\n### SS2 Next Steps\nA future goal is to allow for CW305 targets which use both the parallel\nSAM3U USB interface **and** UART (such as our\n[DesignStartTrace](https://github.com/newaetech/DesignStartTrace)) by\nexpanding the SS2 wrapper to allow encapsulating UART commands inside SS2\ncommands.\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnewaetech%2Ffpga-common","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fnewaetech%2Ffpga-common","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnewaetech%2Ffpga-common/lists"}