{"id":17431988,"url":"https://github.com/nic30/hdlconvertorast","last_synced_at":"2025-04-09T13:10:18.723Z","repository":{"id":57437013,"uuid":"262299509","full_name":"Nic30/hdlConvertorAst","owner":"Nic30","description":"Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator","archived":false,"fork":false,"pushed_at":"2024-10-23T18:28:58.000Z","size":735,"stargazers_count":31,"open_issues_count":3,"forks_count":7,"subscribers_count":3,"default_branch":"master","last_synced_at":"2024-10-24T04:02:51.263Z","etag":null,"topics":["codegen","codegenerator","fpga","python","systemc","systemverilog","verilog","vhdl"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Nic30.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-05-08T10:55:30.000Z","updated_at":"2024-10-23T18:29:03.000Z","dependencies_parsed_at":"2024-10-26T15:15:45.848Z","dependency_job_id":"090f5aa7-4cc2-4ab7-b5aa-4d05d72dc050","html_url":"https://github.com/Nic30/hdlConvertorAst","commit_stats":{"total_commits":499,"total_committers":4,"mean_commits":124.75,"dds":"0.014028056112224463","last_synced_commit":"3dbd1acc12be8e2a9538e1e9636519dfe81be864"},"previous_names":[],"tags_count":12,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Nic30%2FhdlConvertorAst","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Nic30%2FhdlConvertorAst/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Nic30%2FhdlConvertorAst/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Nic30%2FhdlConvertorAst/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Nic30","download_url":"https://codeload.github.com/Nic30/hdlConvertorAst/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248045245,"owners_count":21038554,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["codegen","codegenerator","fpga","python","systemc","systemverilog","verilog","vhdl"],"created_at":"2024-10-17T08:09:38.868Z","updated_at":"2025-04-09T13:10:18.693Z","avatar_url":"https://github.com/Nic30.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"# hdlConvertorAst\n[![CircleCI](https://circleci.com/gh/Nic30/hdlConvertorAst.svg?style=svg)](https://circleci.com/gh/Nic30/hdlConvertorAst)\n[![PyPI version](https://badge.fury.io/py/hdlConvertorAst.svg)](http://badge.fury.io/py/hdlConvertorAst)\n[![Python version](https://img.shields.io/pypi/pyversions/hdlConvertorAst.svg)](https://img.shields.io/pypi/pyversions/hdlConvertorAst.svg)\n[![Coverage Status](https://coveralls.io/repos/github/Nic30/hdlConvertorAst/badge.svg?branch=master)](https://coveralls.io/github/Nic30/hdlConvertorAst?branch=master)\n[![Documentation Status](https://readthedocs.org/projects/hdlconvertorast/badge/?version=latest)](https://hdlconvertorast.readthedocs.io/en/latest/?badge=latest)\n \nThis library contains universal [HDL AST nodes](https://github.com/Nic30/hdlConvertorAst/tree/master/hdlConvertorAst/hdlAst/__init__.py) (Hardware Description Language Abstract Syntax Tree = objects for representation of code constructs) for SystemVerilog, VHDL and others. This AST can be generated from SV/VHDL code by [hdlConvertor](https://github.com/Nic30/hdlConvertor) and it can also be converted to VHDL/SV/JSON/SystemC/... and other formats using [hdlConvertorAst.to module](https://github.com/Nic30/hdlConvertorAst/tree/master/hdlConvertorAst/to).\nNote that the conversion of AST of different languages requires an extra care.\nE. g. the VHDL AST and SV AST will have a different type names and thus the direct transpilation using [hdlConvertorAst.to module](https://github.com/Nic30/hdlConvertorAst/tree/master/hdlConvertorAst/to) will not yield working code. If source and target language differs the translation is required. For this translations and post processing you can use [hdlConvertorAst.translate module](https://github.com/Nic30/hdlConvertorAst/tree/master/hdlConvertorAst/translate)\n\nDoc shared with [hdlConvertor](https://github.com/Nic30/hdlConvertor).\n\n### Intended as a support library for\n  * code generators\n  * code parsers\n  * compilers/transpilers\n\n### Supported languages\n  * [IEEE 1076-2008 (VHDL 2008)](https://ieeexplore.ieee.org/document/4772740) and all previous standard, (currently without `tool_directive` and `PSL`)\n  * [IEEE 1800-2017 (SystemVerilog 2017)](https://ieeexplore.ieee.org/document/8299595) and all previous standards.\n  * SystemC 2.3.3\n  * HdlConvertor JSON\n  * hwtSimApi basic_rtl_sim_model (python interpreted RTL simulator)\n  * hwt (hardware construction framework (HCL) with algorithmic synthesis (HLS))\n\n\n### List of selected unique features of this library\n  * single straightforward universal AST for all languages, wide spectrum of import/export languages\n  * automatic parenthesis resolution in expressions based on operator priority/associativity\n  * clever white-spaces, constant and expression formating \n  * comments preserved as doc of objects\n\n### Installation\n\n```bash\n# note this may be older version than you see in repo\nsudo pip3 install hdlConvertorAst\n\n# or download repository and run\nsudo python3 setup.py install\n\n# if you are using version from git rather uninstall\n# old library first if required\n# sudo pip3 uninstall hdlConvertorAst\n```\n\n### Similar projects\n\n   * [fasm](https://github.com/SymbiFlow/fasm) - Python, FPGA Assembly (FASM) Parser and Generator  \n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnic30%2Fhdlconvertorast","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fnic30%2Fhdlconvertorast","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnic30%2Fhdlconvertorast/lists"}