{"id":23784898,"url":"https://github.com/nishit0072e/2bit-comparator","last_synced_at":"2026-02-25T09:41:48.007Z","repository":{"id":266704514,"uuid":"899101840","full_name":"nishit0072e/2bit-Comparator","owner":"nishit0072e","description":"2 bit comparator design in transistor level in eSim software foremerly FreeCAD","archived":false,"fork":false,"pushed_at":"2024-12-05T16:22:30.000Z","size":382,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-11-11T09:10:25.325Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"TL-Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/nishit0072e.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-12-05T16:14:14.000Z","updated_at":"2024-12-05T16:22:34.000Z","dependencies_parsed_at":"2024-12-05T17:34:08.054Z","dependency_job_id":null,"html_url":"https://github.com/nishit0072e/2bit-Comparator","commit_stats":null,"previous_names":["nishit0072e/2bit-comparator"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/nishit0072e/2bit-Comparator","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nishit0072e%2F2bit-Comparator","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nishit0072e%2F2bit-Comparator/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nishit0072e%2F2bit-Comparator/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nishit0072e%2F2bit-Comparator/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/nishit0072e","download_url":"https://codeload.github.com/nishit0072e/2bit-Comparator/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nishit0072e%2F2bit-Comparator/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29816252,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-25T05:36:42.804Z","status":"ssl_error","status_checked_at":"2026-02-25T05:36:31.934Z","response_time":61,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2025-01-01T13:13:23.070Z","updated_at":"2026-02-25T09:41:47.989Z","avatar_url":"https://github.com/nishit0072e.png","language":"TL-Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# 2-bitcomparator_mixedsignal_esim_SKY130\n## Contents\n- [Abstract](#abstract)\n- [Circuit Details](#circuit-details)\n- [Truth Table](#truth-table)\n- [Software Used](#software-used)\n- [Steps to run generate NgVeri Model](#steps-to-run-generate-ngveri-model)\n\n\n## Abstract\nA Comparator is a combinational\ncircuit that compares two binary numbers in order to find\nout whether one binary number is equal, less than, or\ngreater than the other binary number. The Circuit will have two inputs one for A and the other for B and have three output terminals, \none for A \u003e B condition,\none for A = B condition, and one for A\u003cB condition.\n## Circuit Details\nIn the diagram, a 2-bit magnitude comparator is split into two blocks: digital and analog.\n\u003c/br\u003e\nThe digital portion of the circuit is implemented using Verilog.\n\u003c/br\u003e\nFor the analog portion, the two 3-input ”OR” gates and one 2-input ”AND” gate are replaced with NMOS and\nPMOS transistors, making the circuit mixed-signal.\n\u003c/br\u003e\nThe output of the mixed signal 2-bit comparator\ncircuit may be less than, equal to (ET), or greater than.                  \n## Truth Table\n\n| Input A1  | Input A0 | Input B1  | Input B0 | Output A\u003cB | Output A=B | Output A\u003eB |\n| ------------- | ------------- | ------------- | ------------- | ------------- | ------------- | ------------- |\n| 0  | 0 | 0  | 0 | 0 | 1  | 0  |\n| 0  | 0 | 0  | 1 | 1 | 0  | 0  |\n| 0  | 0 | 1  | 0 | 1 | 0  | 0  |\n| 0  | 0 | 1  | 1 | 1 | 0  | 0  |\n| 0  | 1 | 0  | 0 | 0 | 0  | 1  |\n| 0  | 1 | 0  | 1 | 0 | 1  | 0  |\n| 0  | 1 | 1  | 0 | 1 | 0  | 0  |\n| 0  | 1 | 1  | 1 | 1 | 0  | 0  |\n| 1  | 0 | 0  | 0 | 0 | 0  | 1  |\n| 1  | 0 | 0  | 1 | 0 | 0  | 1  |\n| 1  | 0 | 1  | 0 | 0 | 1  | 0  |\n| 1  | 0 | 1  | 1 | 1 | 0  | 0  |\n| 1  | 1 | 0  | 0 | 0 | 0  | 1  |\n| 1  | 1 | 0  | 1 | 0 | 0  | 1  |\n| 1  | 1 | 1  | 0 | 0 | 0  | 1  |\n| 1  | 1 | 1  | 0 | 0 | 0  | 1  |\n| 1  | 1 | 1  | 1 | 0 | 1  | 0  |\n## Software Used\n### eSim 2.3\nIt is an Open Source EDA developed by FOSSEE, IIT Bombay. It is used for electronic circuit simulation. It is made by the combination of two software namely NgSpice and KiCAD.\n\u003c/br\u003e\nFor more details refer:\n\u003c/br\u003e\nhttps://esim.fossee.in/home\n### NgSpice\nIt is an Open Source Software for Spice Simulations. For more details refer:\n\u003c/br\u003e\nhttp://ngspice.sourceforge.net/docs.html\n### Makerchip\nIt is an Online Web Browser IDE for Verilog/System-verilog/TL-Verilog Simulation. Refer\n\u003c/br\u003e https://www.makerchip.com/\n\n## Circuit Diagram in eSim\nThe following is the schematic in eSim:\n![comparator_circuit](https://user-images.githubusercontent.com/100477948/194511170-a0571262-7556-4d2a-a240-75bb049d6cd2.png)\n## Steps to run generate NgVeri Model\n1. Open eSim\n2. Run NgVeri-Makerchip \n3. Add top level verilog file in Makerchip Tab\n4. Click on NgVeri tab\n5. Add dependency files\n6. Click on Run Verilog to NgSpice Converter\n7. Debug if any errors\n8. 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