{"id":20850436,"url":"https://github.com/noteed/riscv-hello-asm","last_synced_at":"2025-05-12T04:31:26.727Z","repository":{"id":55523329,"uuid":"186496970","full_name":"noteed/riscv-hello-asm","owner":"noteed","description":"Bare metal RISC-V assembly hello world","archived":false,"fork":false,"pushed_at":"2021-10-16T12:08:54.000Z","size":21,"stargazers_count":35,"open_issues_count":1,"forks_count":7,"subscribers_count":3,"default_branch":"main","last_synced_at":"2023-04-13T10:31:56.633Z","etag":null,"topics":["assembly","riscv"],"latest_commit_sha":null,"homepage":"","language":"Assembly","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/noteed.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2019-05-13T21:17:36.000Z","updated_at":"2023-04-12T16:40:47.000Z","dependencies_parsed_at":"2022-08-15T02:20:43.749Z","dependency_job_id":null,"html_url":"https://github.com/noteed/riscv-hello-asm","commit_stats":null,"previous_names":[],"tags_count":null,"template":null,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/noteed%2Friscv-hello-asm","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/noteed%2Friscv-hello-asm/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/noteed%2Friscv-hello-asm/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/noteed%2Friscv-hello-asm/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/noteed","download_url":"https://codeload.github.com/noteed/riscv-hello-asm/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":225120017,"owners_count":17423818,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["assembly","riscv"],"created_at":"2024-11-18T03:09:30.431Z","updated_at":"2024-11-18T03:09:31.207Z","avatar_url":"https://github.com/noteed.png","language":"Assembly","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Bare metal RISC-V assembly hello world\n\nThis is a bare metal 64-bit RISC-V assembly program outputing `Hello.`. It is\ncompiled with the riscv-gnu-toolchain and can be run with the QEMU `sifive_u`\nand `sifive_e` machines.\n\nI searched for such a program on the Internet but the only examples I found\nwere either bare metal C, or assembly but relying on an OS. Eventually I took\nthe bare metal hello program from the\n[riscv-probe](https://github.com/michaeljclark/riscv-probe) repository and\nstripped everything I could. [The\nresult](https://github.com/noteed/riscv-hello-c) can be disassembled and serve\nas a guide to adapt other hello world examples.\n\n\n## Toolchain\n\nI'm using Nix and use a toolchain provided by Nixpkgs's [cross-compiling\ninfrastructure](https://nixos.wiki/wiki/Cross_Compiling). This repository\ncontains a `shell.nix` file, and the example commands in this README can be\nfollowed with either `nix-shell --attr riscv64` for the `sifive_u` case, or\n`nix-shell --attr riscv32` for the `sifive_e` case.\n\nSomeone seems to have success with the SiFive binaries as seen in [the first\nissue](https://github.com/noteed/riscv-hello-asm/issues/1).\n\n\n## Building for the `sifive_u` machine\n\nAssuming the toolchain is in the `$PATH`, running the following produces our\n`hello` program.\n\n```\n$ riscv64-unknown-linux-gnu-gcc -march=rv64g -mabi=lp64 -static -mcmodel=medany \\\n  -fvisibility=hidden -nostdlib -nostartfiles -Tsifive_u/hello.ld -Isifive_u \\\n  hello.s -o hello\n```\n\nThe result is a 64-bit RISC-V binary compatible with QEMU `sifive_u` machine.\n\n```\n$ file hello\nhello: ELF 64-bit LSB executable, UCB RISC-V, version 1 (SYSV), statically\nlinked, not stripped\n```\n\nRun it with:\n\n```\n$ qemu-system-riscv64 -nographic -machine sifive_u -bios none -kernel hello\nHello.\nQEMU: Terminated\n```\n\nNote: the program enters an infinite loop after producing the `Hello.` text.\nType `ctrl-a x` to stop QEMU.\n\n\n## Building for the `sifive_e` machine\n\nThis program can be compiled for more resticted machines like `sifive_e`\nthat support 32-bit RISC-V, have small amount of RAM and require executable\ncode to be placed in ROM with different start address.\n\nAssuming the toolchain is in the `$PATH`, running the following produces our\n`hello` program, but now ready for `sifive_e`.\n\n```\n$ riscv32-none-elf-gcc -march=rv32g -mabi=ilp32 -static -mcmodel=medany \\\n  -fvisibility=hidden -nostdlib -nostartfiles -Tsifive_e/hello.ld -Isifive_e \\\n  hello.s -o hello\n```\n\nNote: using either `riscv32-none-elf-gcc` or `riscv64-unknown-linux-gnu-gcc`\nworks.\n\nRun it with:\n\n```\n$ qemu-system-riscv32 -nographic -machine sifive_e -bios none -kernel hello\nHello.\nQEMU: Terminated\n```\n\nNote: the program enters an infinite loop after producing the `Hello.` text.\nType `ctrl-a x` to stop QEMU.\n\n\n## Assembly\n\nTo disassemble the program (here the one for the `sifive_u` machine):\n\n\n```\n$ riscv64-unknown-elf-objdump -d hello\nhello:     file format elf64-littleriscv\n\n\nDisassembly of section .text:\n\n0000000080000000 \u003c_start\u003e:\n    80000000:\tf14022f3         csrr\tt0,mhartid\n    80000004:\t00029c63         bnez\tt0,8000001c \u003chalt\u003e\n    80000008:\t00008117         auipc\tsp,0x8\n    8000000c:\t04410113         addi\tsp,sp,68 # 8000804c \u003c_end\u003e\n    80000010:\t00000517         auipc\ta0,0x0\n    80000014:\t03450513         addi\ta0,a0,52 # 80000044 \u003cmsg\u003e\n    80000018:\t008000ef         jal\tra,80000020 \u003cputs\u003e\n\n000000008000001c \u003chalt\u003e:\n    8000001c:\t0000006f         j\t8000001c \u003chalt\u003e\n\n0000000080000020 \u003cputs\u003e:\n    80000020:\t100102b7         lui\tt0,0x10010\n    80000024:\t00054303         lbu\tt1,0(a0)\n    80000028:\t00030c63         beqz\tt1,80000040 \u003cputs+0x20\u003e\n    8000002c:\t0002a383         lw\tt2,0(t0) # 10010000 \u003cUART_BASE\u003e\n    80000030:\tfe03cee3         bltz\tt2,8000002c \u003cputs+0xc\u003e\n    80000034:\t0062a023         sw\tt1,0(t0)\n    80000038:\t00150513         addi\ta0,a0,1\n    8000003c:\tfe9ff06f         j\t80000024 \u003cputs+0x4\u003e\n    80000040:\t00008067         ret\n```\n\n\n## Elsewhere\n\nHere is a link to another repository that links back to this repository, and\nthat may be worth checking out.\n\n- [Bare metal RISC-V assembly in QEMU](https://github.com/rtfb/riscv64-in-qemu)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnoteed%2Friscv-hello-asm","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fnoteed%2Friscv-hello-asm","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnoteed%2Friscv-hello-asm/lists"}